Sandipan Kundu

A Compact, Supply-Voltage Scalable 45–66 GHz Baseband-Combining CMOS Phased-Array Receiver

This paper presents a four-element phased-array receiver which achieves 38% fractional bandwidth around 55 GHz. Baseband phase-shifting is employed to eliminate wideband phase-shifters, power dividers, and quadrature splitters operating at millimeter-wave frequencies. Antenna weighting and combining are accomplished using a highly digital Cartesian phase-shifter and current summation, respectively. Transformer-coupling techniques are introduced in the LNA to simultaneously achieve wide bandwidth, reduced noise figure, gain boosting and neutralization. Cascode-free and folded topologies are used throughout to enable operation from a scalable supply voltage. To overcome challenges associated with wideband LO distribution, the LO network employs multiconductor transmission lines to distribute four-phase LO signals. The LO distribution network is absorbed into the LO buffers and terminated by distributed LC loads near the I/Q mixers in each phased-array element. The phased-array receiver is fabricated in a 45 nm SOI CMOS process and achieves 26.2 dB (20.2 dB) of element gain over 21 GHz (19 GHz) of 3 dB bandwidth with 5.5 dB/9.8 dB (7.7 dB/12 dB) minimum/maximum NF while dissipating 30 mW/element (14 mW/element) from a 1.1 V (0.6 V) supply voltage. The worst case -1 dB (input) compression is -28 dBm at 1.1 V. A worst case coupling of 26 dB (45 dB) is measured between adjacent (nonadjacent) elements. The IF bandwidth is 1.2 GHz, limited by the wirebond and PCB interface to the chip. The design occupies only 0.225 mm 2 per element including LO buffer/distribution.

A 3/5 GHz reconfigurable CMOS low-noise amplifier integrated with a four-terminal phase-change RF switch

This paper presents the first reported in-situ reconfiguration of a narrowband CMOS low noise amplifier (LNA) over two widely separated frequency bands using a GeTe phase-change (PC) switch. Previous work has demonstrated the attractiveness of CMOS-PC integration to realize high-performance reconfigurable RF front-end circuits [1-2]. Four-terminal PC switches with small form factor have been recently shown to possess close-to-ideal properties of an RF switch: a high OFF/ON resistance ratio and extremely high figure-of-merit for RF switches (FCO = 1/(2πRONCOFF)) [3-4]. In this work, we present a robust realization of a reconfigurable 3/5 GHz LNA designed and fabricated in a 0.13 μm CMOS process and flip-chip integrated with a four-terminal PC switch fabricated using an in-house process.

A 17 GHz transformer-neutralized current re-use LNA and its application to a low-power RF front-end

A 17 GHz current re-use low noise amplifier (LNA) is designed in 0.13 µm CMOS for low power applications such as wireless sensor networks. The LNA also employs transformer based feedback to neutralize the gate-drain capacitance of a MOSFET. The LNA achieves 15.4 dB gain into a 50 Ω load along with 1.9 GHz bandwidth. It features 4.5dB NF and −12 dBm IIP3 while consuming 7.8 mW of power. A 17 GHz receiver frontend using a similar two-stage LNA and a mixer is also demonstrated which achieves 25 dB of voltage conversion gain at 70 MHz IF, 7 dB NF, −18 dBm IIP3 and consumes 8 mW from a 1.2 V supply.

A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN

A clock-skew tolerant 8-bit 16x time-interleaved (TI) semi-synchronous SAR ADC with switching-energy efficient hybrid resistive-capacitive DAC is presented that meets WiGig standard requirements with only background offset and gain calibrations. Skew tolerance is achieved by using a “correct-by-construction,” timing-calibration-free global bottom-plate sampling scheme. The ADC achieves a sampling rate of 2.64 GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40 nm LP CMOS design dissipates 39 mW from 1.2 V. The TI-SAR ADC characterized with an integrated receiver front-end achieves -21.44 dB EVM at sensitivity with a QAM16 signal.

Frequency-Channelized Mismatch-Shaped Quadrature Data Converters for Carrier Aggregation in MU-MIMO LTE-A

Emerging wireless standards aggregate information by selecting combinations of contiguous or non-contiguous channels, thereby enabling wider transmission bandwidths, and hence, higher data rates. Frequency-interleaved analog-to-digital conversion (FI-ADC) is an attractive emerging technique for carrier aggregation receivers because it facilitates an efficient way to dynamically vary the receiver bandwidth in order to address the many possible channel combinations. Compared to their time-interleaved counterparts, the specifications of the samplers in the parallel channels in FI-ADCs are significantly relaxed, thereby resulting in lower overall power consumption in the receiver. This work extends the FI-ADC concept to the quadrature frequency-interleaved oversampled data converter (QFI-ADC) to achieve greater aggregate data rates. Previously, digital-to-analog converter (DAC) and other inter-channel mismatches have limited the performance of QFI-ADCs. In this paper, we propose a low-complexity element rotation algorithm (ERA) to mitigate DAC mismatches. The ERA is synthesized from the corresponding mismatch transfer function using a rigorous mathematical procedure which is shown to be applicable generally to low-pass, high-pass, band-pass and quadrature ERAs. Simulations confirm that the resulting low-complexity quadrature ERAs have advantages over previously proposed approaches in both performance and hardware complexity. An additional gain calibration technique alleviates image folding due to gain and timing mismatches between the quadrature DAC elements, which yields higher SNDR.

A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN

A clock-skew tolerant 8-bit 16x time-interleaved (TI) SAR ADC is presented that meets WiGig standard requirements with only background offset and gain calibrations. By using a “correct-by-construction”, timing-calibration-free global bottom-plate sampling scheme, the ADC achieves a sampling rate of 2.64GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40nm LP CMOS design dissipates 39mW from 1.2V. The TI-SAR ADC characterized with an integrated receiver front-end achieves -21.44dB EVM at sensitivity with an OFDM/ QAM16 signal.

A supply-voltage scalable, 45 nm CMOS ultra-wideband receiver for mm-wave ranging and communication

A supply-voltage scalable, low-power, millimeter-wave UWB receiver fabricated in 45nm SOI CMOS is presented. All stages in the LNA and the quadrature mixers are limited to a single transistor in the stack between supply and ground, thereby allowing supply voltage scalability. A transformer neutralization technique is introduced for CG and CS stages to mitigate the deleterious effect of reverse signal flow. This ensures stable, unilateral operation over the entire bandwidth. The receiver achieves 46-64 GHz (48-68 GHz) bandwidth, 24.5 dB (20.7 dB) conversion gain, 5.3 dB (7.8 dB) NF and -22 dBm (-21.7 dBm) P1dB from a 1.1 V (0.6 V) supply voltage while consuming 18.4 mW (7 mW) power.

Adaptive Beamforming Assisted Decision Feedback Equalization for Millimeter Wave Receivers

Beamforming and equalization are two key, but power hungry functions, essential in a mm-wave receiver. This paper proposes the incorporation of null adaptation and beam steering into the beamformer in order to reduce the length of the time-domain equalizer. The adaptive beamformer spatially filters the received signal field by steering main beam towards the angle of arrival of desired signal and steering nulls towards the angle of arrival of strong multipath components, thereby reducing their adverse effects prior to the DFE. This, in turn, significantly reduces the complexity and hence the power consumption of the DFE. The development of this architecture is closely guided by hardware considerations; in particular, the spatial processing hardware is implemented in the analog baseband domain, while the feedback equalizer is implemented using mixed analog-digital hardware. Adaptation circuitry is implemented using mostly digital hardware. Using this technique, higher data rates can be supported with a given number of elements. Conversely, the number of antennas and/or equalizer taps may be decreased while meeting a given data rate target. Extensive simulations using real mm-wave channel models are presented to support these hypotheses.

Low-power front-end amplification and frequency generation techniques for ultra-wideband millimeter-wave transceivers

This paper presents low-power design techniques for wideband LNAs and wide-tuning frequency generation circuits operating at mm-wave. Transformer neutralization techniques enable the design of current-reuse and low-voltage LNAs. Transformer-based VCOs with resonance mode switching are introduced to achieve very wide tuning range. The design and characterization of several prototype circuits is presented to validate these concepts.