Jhe-Jia Kuo

A DC-11.5 GHz Low-Power, Wideband Amplifier Using Splitting-Load Inductive Peaking Technique

A DC-11.5 GHz low-power amplifier is developed in commercial 0.13 mum, CMOS technology. This amplifier design is based on a three-stage shunt-feedback inverter-configuration with splitting load inductive peaking technique. The peaking inductor is placed at the gate of the nMOS to compensate gain roll-off of the inverter stage and extend its operating bandwidth. This amplifier achieves a gain flatness of 13.21 dB from dc to 11.5 GHz with I/O return losses better than 17 dB at a power consumption of 9.1 mW. The measured noise figure is less than 5.6 dB between 1-11 GHz. The output P1 dB is 8 dBm and input third-order intercept point is 10 dBm. The total chip size is 0.34 mm2 including all testing pads, with a core area of only 0.08 mm2.

A 50 GHz Divide-by-4 Injection Lock Frequency Divider Using Matching Method

A fully integrated divide-by-4 frequency divider has been designed, fabricated, and measured in the standard bulk 0.18-m complementary metal-oxide semiconductor (CMOS) technology. A newly proposed matching technique was used to eliminate the unwanted low frequency mixing terms at the common node of the circuit so as to achieve a high division ratio of 4. The frequency divider exhibits a measured operation range of 5 GHz from 45.9 to 50.9 GHz. It consumes a dc power of 7.56 mW at a 1.2 V supply in the steady state operation. The phase noise of the free running divider is 88.51 dBc/Hz at 1 MHz offset and the locked divider is 110.74 dBc/Hz at 1 MHz offset. The chip size is only 0.35 mm 0.5 mm including the pad frame. To our knowledge, this divider has the highest operation frequency to date among the high division ratio injection-lock type frequency dividers in commercial CMOS 0.18-m process.

A 60–110 GHz Transmission-Line Integrated SPDT Switch in 90 nm CMOS Technology

This letter demonstrates a fully integrated transmit/receive single-pole-double-throw switch in standard bulk 90 nm CMOS process. This switch is based on the transmission-line integrated approach that reduces the effect of parasitic capacitance of transistors in the desired band, and this approach can achieve good isolation and return loss with fewer stages of transistors and broad bandwidth. The switch provides an insertion loss of 3-4 dB and a return loss better than 10 dB in 60-110 GHz. The measured isolation is better than 25 dB. The measured 1 dB compression point of input power is 10.5 dBm at 75 GHz. To the best of our knowledge, this is the first CMOS switch operating beyond 100 GHz.

Design and Analysis of Down-Conversion Gate/Base-Pumped Harmonic Mixers Using Novel Reduced-Size 180

In this paper, a novel 180°hybrid with different input frequencies is proposed to combine RF and local oscillator (LO) signals with different frequencies in a gate/base-pumped harmonic mixer. The detailed analysis and design procedures are presented in this paper. To further reduce the chip size, the multilayer metallization above the lossy silicon substrate is employed to implement the hybrid. A V-band down-converted 2× harmonic mixer in 90-nm CMOS process and a D-band down-converted 4× harmonic mixer in the 130-nm SiGe process are designed, fabricated, and measured to verify the concept. The 2× harmonic mixer possesses 0-dB conversion gain at 60 GHz with 0-dBm LO power with merely 2.4-mW dc power. The 4× harmonic mixer achieves 0.5-dB conversion gain at 120 GHz with 2-dBm LO power and 27.3-mW dc power. With the proposed reduced-size 180° hybrid, gate/base-pumped harmonic mixers are very attractive in transceivers demanding low LO frequency and power.

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This letter demonstrates a 22-31 GHz CMOS distributed amplifier (DA) based on high-pass transmission lines. Unlike the low-pass DA, the circuit can be smaller since it does not need extra drain bias circuits. This DA has a maximum output power of 12 dBm, a maximum OP1dB of 6.5 dBm, and a small signal gain of 6.4 dB. The chip occupies a miniature area of 0.28 mm2 including the pads and the core area is only 0.17 mm2.

Hybrid With Different Input Frequencies

In this paper, a high-gain and wideband low-noise amplifier using 65-nm CMOS process is proposed. A four-stage cascode configuration is adopted to achieve the high gain and wideband performance. With 24-mA dc current and 2-V supply voltage, the LNA not only provides gain higher than 20 dB from 75.5 GHz to 120.5 GHz, but also has a measured noise figure between 6 and 8.3 dB from 87 to 100 GHz. The output 1-dB compression power (OP1dB) is −3 dBm at 110 GHz, and the chip size is 0.55 × 0.45 mm2.

A 22–31 GHz Distributed Amplifier Based on High-Pass Transmission Lines Using 0.18

This paper presents a chip set of RF front-end circuits using 65-nm CMOS technology. The chip set includes a LNA, a down-conversion mixer, an up-conversion mixer and a medium power amplifier. The LNA has the 3-dB bandwidth from 68 to 75 GHz with a peak value of 17 dB. The down-conversion mixer has a conversion loss of better than −5 dB from 53 to 73 GHz at 4 dBm LO power. The up-conversion mixer has a conversion loss better than −5 dB from 53 to 75 GHz at 6 dBm LO power. The medium power amplifier delivers 5 dBm P1dB and 6.7 dBm Psat at 71 GHz. These results show the potential of the 65-nm CMOS technology in high frequency circuit design.

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A 60-GHz vector sum phase shifter with single-ended-to-differential function for phased array receiver using 90-nm LP CMOS technology is presented. This phase shifter incorporates a four-way quadrature power divider as a vector generator with two variable gain amplifiers and a vector modulator to achieve full-360° phase synthesizing. For 4-bit operation (22.5° phase resolution) from 57–64 GHz, this phase shifter exhibits a gain error and a phase error for all the 16 states of within 2.5 dB and 11°, respectively. The RMS gain error at the two output ports are both under 1.2 dB, and the RMS phase error is under 10.5°. The RMS gain imbalance and phase imbalance between the differential outputs are under 0.8 dB and 5.2°, respectively. The average gain of one of the differential outputs at 60 GHz is −5.4 dB, and the input and output return losses are both over 10 dB. This chip consumes 34 mW from a 1.2-V supply. The chip size including all the pads is 0.96 × 0.69 mm2.

CMOS Technology

Usually the tuning range of voltage controlled oscillator (VCO) is much narrower than the possible resonant frequency range of the tank at different tuning voltages. In this letter we analyze the traditional common-base type VCO, give a simple but useful insight about the mechanism behind the topology, and verified the conclusions with a 2 mum heterojunction bipolar transistor (HBT) VCO. The results show that with the CB configuration, proper feedback inductor and wide tuning range varactor, the tuning range can be almost the same as the resonant frequency range of the tank at different tuning voltages. A wideband voltage controlled oscillator using a commercial 2 mum HBT technology is designed, fabricated and measured. The varactor with wide range of capacitance is used to achieve 53.33% measured tuning range from 9.46 to 16.34 GHz. The measured phase noise at 1 MHz offset is between -90 and -102 dBc/Hz. The total chip size is 1 mm2 including all testing pads, while the core area is 0.64 mm2. The VCO is suitable for wideband application such as in measurement equipment or astronomical exploring telescopes.

A 75.5-to-120.5-GHz, high-gain CMOS low-noise amplifier

A 57–64 GHz current-steering variable-gain amplifier (VGA) with low-phase-variation characteristics is presented in this paper. The phase analysis of current-steering topology reveals the effect of the phase compensation capacitor. The proposed VGA achieves peak gain of 13–15 dB from 57–67 GHz, and the phase variation is lower than 6.6° within 15.5-dB gain control range (GCR) in the desired band. The dc power consumption is 36 mW from 2-V supply voltage.