Jiale Liang

Phase Change Memory

In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies

Cross-point memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable array size. In this paper, we study the device requirements of a resistive cross-point memory array under the worst-case write and read operations. We focus on the data pattern dependence of the memory array and compare the effect of the memory cell resistance values and resistance ratio for determining the maximum array size. The number of cells in the array can reach 106 with a signal swing > 50% of the reading voltage when Ron is beyond 3 M and Roff/Ron is greater than 2. A large memory cell resistance value can further reduce the power consumption, obviate the need for a large Roff/Ron ratio, and avoid the inclusion of cell selection devices. The effect of the nonlinearity of the I -V characteristics of the memory cells is also investigated. The nonlinearity calls for a substantial tradeoff between the memory cell resistance values and the resistance ratio, and must be taken into consideration for the device design.

Monitoring Oxygen Movement by Raman Spectroscopy of Resistive Random Access Memory with a Graphene-Inserted Electrode

In this paper, we employed Ramen spectroscopy to monitor oxygen movement at the electrode/oxide interface by inserting single-layer graphene (SLG). Raman area mapping and single-point measurements show noticeable changes in the D-band, G-band, and 2D-band signals of the SLG during consecutive electrical programming repeated for nine cycles. In addition, the inserted SLG enables the reduction of RESET current by 22 times and programming power consumption by 47 times. Collectively, our results show that monitoring the oxygen movement by Raman spectroscopy for a resistive random access memory (RRAM) is made possible by inserting a single-layer graphene at electrode/oxide interface. This may open up an important analysis tool for investigation of switching mechanism of RRAM.

Read/write schemes analysis for novel complementary resistive switches in passive crossbar memory arrays

Recently a prototype of complementary resistive switches has been proposed to solve the sneak-path problem in passive crossbar memory arrays. To further evaluate the potential of this novel cell structure for practical applications, we present a modeling analysis to capture its switching dynamics and analyze its unique read/write schemes. The model is corroborated by experimental data. We found a trade-off between the read voltage window and write voltage window. The constraint from avoiding disturbance on unselected cells is critical for proper functionality, which in turn limits the writing speed.

An Ultra-Low Reset Current Cross-Point Phase Change Memory With Carbon Nanotube Electrodes

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 μA and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology.

Analytical ballistic theory of carbon nanotube transistors: Experimental validation, device physics, parameter extraction, and performance projection

We developed a fully analytical ballistic theory of carbon nanotube field effect transistors enabled by the development of an analytical surface potential capturing the temperature dependence and gate and quantum capacitance electrostatics. The analytical ballistic theory is compared to the experimental results of a ballistic transistor with good agreement. The validated analytical theory enables intuitive circuit design, provides techniques for parameter extraction of the bandgap and surface potential, and elucidates on the device physics of drain optical phonon scattering and its role in reducing the linear conductance and intrinsic gain of the transistor. Furthermore, a threshold voltage definition is proposed reflecting the bandgap-diameter dependence. Projections for key analog and digital performances are discussed.

Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array

The impact of wordline/bitline metal wire scaling on the write/read performance, energy consumption, speed, and reliability of the cross-point memory array is quantitatively studied for technology nodes down to single-digit nm. The impending resistivity increase in the Cu wires is found to cause significant decrease of both write and read window margins at the regime when electron surface scattering and grain boundary scattering are substantial. At deeply-scaled device dimensions, the wire energy dissipation and wire latency become comparable to or even exceed the intrinsic values of memory cells. The large current density flowing through the wordlines/bitlines raises additional reliability concerns for the cross-point memory array. All these issues are exacerbated at smaller memory resistance values and larger memory array sizes. They thereby impose strict constraints on the memory device design and preclude the realization of large-scale cross-point memory array with minimum feature sizes beyond the 10 nm node. A rethink in the design methodology of cross-point memory to incorporate and mitigate the scaling effects of wordline/bitline is necessary. Possible solutions include the use of memory wires with better conductivity and scalability, memory arrays with smaller partition sizes, and memory elements with larger resistance values and resistance ratios.

Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

Three key advances in device technology must be made to realize the potential of carbon nanotube transistors: (1) aligned CNT density of ≥200 CNT/µm on a wafer scale, (2) stable p- and n-type doping on the same wafer with control over the doping level, (3) low resistance metal to CNT contact at short (<20 nm) contact length. CNFET technology has now advanced to a point where large scale circuit level demonstration can be contemplated. This is made possible by advances in wafer-scale CNT growth, multiple CNT transfer, and imperfection-immune design techniques to overcome mis-positioned CNTs [11] and m-CNTs (e.g. VMR [18–19] and ACCNT [27]). In order to minimize CNT-specific variations (e.g. CNT count variations [45]), circuit design techniques co-optimized with process technology will play an important role. In the near future, CNFET circuit performance demonstration at GHz clock speed with the requisite device density is expected.

High performance germanium n-MOSFET with antimony dopant activation beyond 1×10 20 cm −3

For the first time, high performance Ge nMOSFET is fabricated using laser annealing of ion-implanted antimony (Sb) dopants which provides donor activation beyond 1×10²⁰cm⁻³ in germanium. Record I<inf>on</inf>/I<inf>off</inf> > 10⁵ is demonstrated for n⁺/p junctions combined with significant reduction of contact resistance to 7×10⁻⁷ Ω-cm². Performance projections for ITRS HP 22nm technology node are also discussed.

Scaling Challenges for the Cross-Point Resistive Memory Array to Sub-10nm Node - An Interconnect Perspective

The impact of Cu interconnect scaling on the write/read margin, energy dissipation, speed and reliability of resistive cross-point memory array are quantitatively examined for wire sizes down to the sub-10nm node. The impending resistivity increase due to wire scaling results in significantly degraded write and read windows, substantial interconnect energy, and increased wire latency. The growing current density required for programming exacerbates the Cu electromigration and is a reliability concern for deeply-scaled technology nodes. Performance degradations are strongly dependent on the memory device parameters and memory array sizes: ron below 100KΩ and array size >; 1Mb lead to write margin <; 55%, read margin <; 5%, and wire energy >; 1pJ for wire size smaller than 20 nm. Also, a large ron value can tolerate a small roff/ron ratio, although a too high ron would result in a slow speed. This work points to the importance of a careful device and interconnect co-optimization to meet the performance specifications for cross- point memory arrays at sub-10nm nodes.