Jiashu Chen

A 65 nm CMOS 4-Element Sub-34 mW/Element 60 GHz Phased-Array Transceiver

This paper describes a low power and element-scalable 60 GHz 4-element phased array transceiver implemented in a standard 65 nm CMOS process. Using a 1.2 V supply, the array consumes <;34 mW/element including LO synthesis and distribution. Energy and area efficiency are achieved by utilizing a baseband phase shifting architecture, holistic impedance optimization, and lumped-element based design. Each receiver (RX) element provides 24 dB of gain with an average noise figure (NF) of 6.8 dB while the total saturated output power of the transmitter (TX) is 4.5 dBm. The array achieves 360° of phase shifting range with a worst-case measured phase resolution of 6 bits (TX)/ 5 bits (RX) while maintaining amplitude variations less than ±0.5 dB.

Design of CMOS Power Amplifiers

This paper describes the key technology and circuit design issues facing the design of an efficient linear RF CMOS power amplifier for modern communication standards incorporating high peak-to-average ratio signals. We show that most important limitations arise from the limited breakdown voltage of nanoscale CMOS devices and the large back-off requirements to achieve the required linearity, both of which result in poor average efficiency. Two fundamentally different approaches to tackle these problems are presented along with silicon prototype measurements. In the first approach, transformer power combining and bias-point optimization are used to increase the output power and linearity of the “analog” amplifier. In the second approach, a mixed-signal “digital” polar architecture is employed, wherein the amplitude modulation is formed through an RF DAC structure.

Design Considerations for a Direct Digitally Modulated WLAN Transmitter With Integrated Phase Path and Dynamic Impedance Modulation

A 65-nm digitally modulated polar TX for WLAN 802.11g is fully integrated along with baseband digital filtering. The TX employs dynamic impedance modulation to improve efficiency at back-off powers. High-bandwidth phase modulation is achieved efficiently with an open-loop architecture. Operating from 1.2-V/1-V supplies, the TX delivers 16.8 dBm average power at -28-dB EVM with 24.5% drain efficiency, 22% PAE, 19.3% system efficiency, and 247-mW power consumption including the entire on-chip TX chain; the noise floor is -125 dBm/Hz at 200-MHz offset without external filtering.

A compact 1V 18.6dBm 60GHz power amplifier in 65nm CMOS

One of the remaining challenges in implementing CMOS 60GHz radios is to cover longer communication distance as the high path loss at mm-Wave frequencies demands higher EIRP, which in turn requires considerable design effort on the transmitter. In addition, to comply with the OFDM transmitting mode of the IEEE 802.15.3c standards, the power amplifier (PA) must be capable to handle a peak power level 6∼9dB higher than the average without sacrificing reliability. With the low supply voltage limitation of deeply scaled CMOS technologies, efficient power-combining techniques are essential. Spatial power combining is an attractive solution to meet the EIRP goal, but at the cost of spending extra power on the complex signal distribution and in order to compensate for the phase-shifter loss. Spatial power-combining solutions also occupy larger area due to the requirement of multiple antennas, minimum antenna spacing, and the transmission line feed network. On the other hand, CMOS PAs with on-chip power-combining structures have achieved 18dBm of output power [1–3]. However, all the combiners comprise multiple stages to achieve both impedance transformation and power combining which not only increase the insertion loss and directly degrade the efficiency, but also consume a significant amount of silicon area, rendering them far less appealing for system integration. This paper presents a fully integrated 18.6dBm CMOS PA based on an efficient and compact on-chip power combiner.

A digitally modulated mm-Wave cartesian beamforming transmitter with quadrature spatial combining

With fast-growing demand for high-speed mobile communications and highly saturated spectral usage below 10GHz, mm-Wave frequency bands are emerging as the key playground for future high-data-rate wireless standards. Recent years have witnessed vast technology development on V-band (60GHz) Wireless Personal Area Networks (WPAN) and E-band (80GHz) point-to-point cellular backhauls. However, existing integrated CMOS mm-Wave solutions have relatively poor energy efficiency, especially for the transmitter (TX). This is mainly due to the use of traditional Class-A Power Amplifiers (PAs) that provide good linearity but suffer from low efficiency. In addition, the efficiency of Class-A PAs drop dramatically at power back-offs, making these transmitters even less efficient when conveying non-constant envelope signals. State-of-the-art mm-Wave Class-A PAs show less than 5% efficiency at 6dB back-off [1,2].

A 65nm CMOS 4-element Sub-34mW/element 60GHz phased-array transceiver

This paper describes a low power and element-scalable 60 GHz 4-element phased array transceiver implemented in a standard 65 nm CMOS process. Using a 1.2 V supply, the array consumes <;34 mW/element including LO synthesis and distribution. Energy and area efficiency are achieved by utilizing a baseband phase shifting architecture, holistic impedance optimization, and lumped-element based design. Each receiver (RX) element provides 24 dB of gain with an average noise figure (NF) of 6.8 dB while the total saturated output power of the transmitter (TX) is 4.5 dBm. The array achieves 360° of phase shifting range with a worst-case measured phase resolution of 6 bits (TX)/ 5 bits (RX) while maintaining amplitude variations less than ±0.5 dB.

Design and Analysis of a Stage-Scaled Distributed Power Amplifier

This paper presents the design, analysis, and measurement of a pseudodifferential distributed power amplifier in a 0.13-μm SiGe BiCMOS process. To mitigate the large loaded transmission line loss due to bipolar base resistance, emitter degeneration is used and an optimal small-signal design point is selected for maximum gain-bandwidth product. To enhance the efficiency of distributed amplifiers (DAs), a stage-scaling technique is proposed to utilize more voltage swing while reducing the total current consumption. The output power and efficiency of the amplifier are evaluated as a function of two scaling coefficients. The fabricated distributed power amplifier achieves a small-signal gain of 10 dB and a 3-dB bandwidth of 110 GHz. The measured midband saturated output power is 17.5 dBm with a peak power-added efficiency (PAE) of 13.2% and the 3-dB output power bandwidth is greater than 77 GHz. The amplifier consumes 119 mA from a 3-V supply and occupies an area of 2.08 mm × 1.05 mm. Compared to a uniform nonscaled DA fabricated in the same process, the stage-scaled amplifier achieves the same output power with higher collector efficiency and PAE over the entire measured frequency range.

A CMOS Ku-band single-conversion low-noise block front-end for satellite receivers

This paper presents a Ku-band single-conversion low-noise block (LNB) front-end in a 0.18 µm CMOS technology. The front-end down-converts the input signal from the Ku-band (10.5 − 13 GHz) to the L-band (0.75 − 2.25 GHz). The in-band noise figure is between 2.8 to 4.2 dB. It achieves a gain of 50 dB with ±2 dB variation. The in-band OIP3 is above 17 dBm and output 1-dB compression point is above 9 dBm. The front-end consumes total of 75 mA from a 1.8 V supply. The die area is 0.8×1.8 mm2.

A digitally modulated 2.4GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65nm CMOS

In order to support higher throughputs, the power consumption of 2-to-5GHz Wi-Fi transmitters (TXs) has been continuously rising, and has hence become increasingly problematic for mobile devices. To extend battery life, the TX must be efficient not only at peak power but also at backoff, due to the use of high Peak-to-Average-Power-Ratio (PAPR) OFDM modulation. Many recent works have aimed to enhance PA efficiency at back-off powers [1-4], but relatively few have integrated these techniques into a complete TX system. For example, previous designs employing digital polar or outphasing architectures often realized phase modulation with off-chip instruments. Similarly, while good close-in spectral performance has been shown, far-out spectral images remain problematic for TXs where the PA itself is digitally modulated. Moreover, previous works often do not include overhead from components such as extra DC-DC converters (for multiple PA supplies) or did not implement on-chip matching networks (MN) and/or output baluns, all of which directly affect the overall efficiency of integrated CMOS PAs.

A stage-scaled distributed power amplifier achieving 110GHz bandwidth and 17.5dBm peak output power

This paper presents the design of a pseudo-differential distributed power amplifier in a 0.13µm SiGe BiCMOS process. Based on the newly proposed efficiency enhancing stage-scaling technique, the distributed power amplifier achieves a small-signal bandwidth of 110GHz, a peak saturated output power of 17.5dBm and a peak PAE of 13.2%. The measured 3dB output power bandwidth is greater than 77GHz. The amplifier consumes 119mA from a 3V supply.