Shinwon Kang

A 65 nm CMOS 4-Element Sub-34 mW/Element 60 GHz Phased-Array Transceiver

This paper describes a low power and element-scalable 60 GHz 4-element phased array transceiver implemented in a standard 65 nm CMOS process. Using a 1.2 V supply, the array consumes <;34 mW/element including LO synthesis and distribution. Energy and area efficiency are achieved by utilizing a baseband phase shifting architecture, holistic impedance optimization, and lumped-element based design. Each receiver (RX) element provides 24 dB of gain with an average noise figure (NF) of 6.8 dB while the total saturated output power of the transmitter (TX) is 4.5 dBm. The array achieves 360° of phase shifting range with a worst-case measured phase resolution of 6 bits (TX)/ 5 bits (RX) while maintaining amplitude variations less than ±0.5 dB.

A 260 GHz fully integrated CMOS transceiver for wireless chip-to-chip communication

A fully integrated 260GHz OOK transceiver is demonstrated in 65nm CMOS. Communication at 10Gb/s has been verified over a range of 40 mm. The Tx/Rx dual on-chip antenna array is implemented with half-width leaky wave antennas. Each Tx consists of a quadrupler driven by a class-D-1 PA with a distributed OOK modulator, and outputs +5 dBm of EIRP. The Rx uses a double balanced mixer to down-convert to a V-band IF signal that is amplified with a wideband IF driver and demoduated on-chip.

A 94 GHz mm-Wave-to-Baseband Pulsed-Radar Transceiver with Applications in Imaging and Gesture Recognition

High-resolution mm-wave array beamformers have applications in medical imaging, gesture recognition, and navigation. A scalable array architecture for 3D imaging is proposed in which single-element phase coherent transceiver (TRX) chips, with programmable TX pulse delay capability, are mounted on a common board to realize the array. This paper presents the design of the enabling TRX chip: a highly integrated 94 GHz phase-coherent pulsed-radar with on-chip antennas. The TRX achieves 10 GHz of frequency tuning range and 300 ps of contiguous pulse position control, enabling its usage in the large-array imager with time-domain TX beamforming. The TRX is capable of transmitting and receiving pulses down to 36 ps, translating to 30 GHz of bandwidth. Interferometric measurements show the TRX can obtain single-target range resolution better than 375 μm (limited by equipment). Based on delay measurements, the time of arrival rms error would be less than 1.3 ps which, if used in a 3D imaging array, leads to less than 0.36 mm of RMS error in voxel size and position.

A 65nm CMOS 4-element Sub-34mW/element 60GHz phased-array transceiver

This paper describes a low power and element-scalable 60 GHz 4-element phased array transceiver implemented in a standard 65 nm CMOS process. Using a 1.2 V supply, the array consumes <;34 mW/element including LO synthesis and distribution. Energy and area efficiency are achieved by utilizing a baseband phase shifting architecture, holistic impedance optimization, and lumped-element based design. Each receiver (RX) element provides 24 dB of gain with an average noise figure (NF) of 6.8 dB while the total saturated output power of the transmitter (TX) is 4.5 dBm. The array achieves 360° of phase shifting range with a worst-case measured phase resolution of 6 bits (TX)/ 5 bits (RX) while maintaining amplitude variations less than ±0.5 dB.

A 90 GHz Hybrid Switching Pulsed-Transmitter for Medical Imaging

This paper reports a fully integrated 90 GHz-carrier pulsed transmitter in 0.13 μm SiGe BiCMOS process for imaging applications. To obtain ultra-short programmable pulses, the transmitter employs a number of novel techniques including hybrid switching and Antentronics. The transmit path includes a quadrature VCO, PA driver, PA and the on-chip folded slot antenna. High speed ECL circuits generate and provide the short pulses in several operating modes. The transmitter achieves a record pulsewidth of 26 ps in the hybrid mode and 33 ps in the independent mode. This translates to >30 GHz of RF BW in the transmitter.

A 0.38 THz Fully Integrated Transceiver Utilizing a Quadrature Push-Push Harmonic Circuitry in SiGe BiCMOS

A fully integrated transceiver operating at 0.38 terahertz (THz) has been demonstrated in 0.13 μm SiGe BiCMOS with fT = 230 GHz. We present a quadrature push-push harmonic circuitry consisting of the clamping pairs driven by balanced quadrature LO signals coupled through the transformers and the Coplanar Stripline (CPS). Harmonic generation of the clamping circuit is analyzed with a clamped sinusoidal model. Several terahertz circuits such as a quadrupler, a THz subharmonic mixer, and an IQ quadrature generator are implemented with the quadrature push-push circuitry to realize a homodyne FMCW radar. Radar functionality is demonstrated with ranging and detection of a target at 10 cm. The measured Equivalent Isotropically Radiated Power (EIRP) of the transmitter is -11 dBm at 0.38 THz and the receiver noise figure (NF) is between 35-38 dB while dissipating a power of 380 mW.

A W-Band Low-Noise PLL With a Fundamental VCO in SiGe for Millimeter-Wave Applications

A W-band fundamental phase-locked loop (PLL) is designed and fully integrated to achieve high output power and low noise in a 0.13-μm SiGe BiCMOS process. A PLL with a fundamental voltage-controlled oscillator (VCO) is chosen after comparing several frequency-synthesizer architectures. Local oscillator (LO) generation and LO distribution are also considered. The employed free-running VCO achieves a tuning range from 92.5 to 102.5 GHz (8.3%), an output power of 6 dBm, and a phase noise of -124.5 dBc/Hz at 10-MHz offset. The locking range of the PLL is from 92.7 to 100.2 GHz, and the phase noise is -102 dBc/Hz at 1-MHz offset. The root mean square jitter integrated from 1 MHz to 1 GHz is 71 fs. Finally, the figure-of-merit for VCOs is discussed.

A 240 GHz Fully Integrated Wideband QPSK Receiver in 65 nm CMOS

Operation at millimeter-wave/sub-terahertz frequencies allows one to realize very high data-rate transceivers for wireless chip-to-chip communication. In this paper, a 240 GHz 16 Gbps QPSK receiver is demonstrated in 65 nm CMOS technology. The receiver employs a direct-conversion mixer-first architecture with an integrated slotted loop antenna. A 240 GHz LO chain drives the passive mixers to down-convert the modulated data to baseband. The baseband signal is then amplified using high gain, wide bandwidth amplifiers. The receiver has a noise figure of 15 dB with a conversion gain of 25 dB calculated from measurement data. The receiver achieves a data rate of 10 Gbps (with ) and a maximum data rate of 16 Gbps (with BER of 10-4) with a receiver efficiency of 16 pJ/bit.

A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS

In this paper, a 240 GHz 16 Gbps QPSK transmitter is demonstrated in 65 nm bulk CMOS process. The transmitter chain employs an 80 GHz local oscillator and a modulator to generate the data that is amplified by a class-E switching power amplifier. The amplified signal then drives the 240 GHz tripler to generate the required modulated data. By using on-chip slotted loop antennas, the transmitter achieves an EIRP of 1 dBm. A maximum data rate of 16 Gbps is achieved with a transmitter efficiency of 14 pJ/bit.

A 240GHz wideband QPSK transmitter in 65nm CMOS

This paper demonstrates a 240GHz wideband QPSK transmitter in 65nm bulk CMOS. The proposed transmitter employs an 80GHz local oscillator, a quadrature differential hybrid, and a QPSK modulator. Additionally, an 80GHz class-E switching power amplifier is used to efficiently boost the phase-modulated wideband signal. A frequency tripler then regenerates the modulated signal at 240GHz while preserving the QPSK constellation. By using on-chip slotted loop antennas, the transmitter achieves an EIRP of 1dBm. A maximum data rate of 16Gbps is achieved with a total power consumption of 220mW.