Murugesan Mariappan

Replacing the PECVD-SiO 2 in the through-silicon via of high-density 3D LSIs with highly scalable low cost organic liner: Merits and demerits

A novel approach to suppress the conventional Cu-TSV induced thermo-mechanical stress in 3D-LSI chip is proposed, fabricated and tested. In this approach, a thermal-chemical-vapor-deposition grown organic poly-imide based polymer is conformally deposited along the side wall of the TSV. As-grown polymer was tested for its physical properties and mechanical properties, and was also evaluated for their role in minimizing the thermo-mechanical stress in vicinal and via-space Si. It was found that replacing the conventional SiO2 dielectric liner (sandwiched between the via-metal and Si) with organic polymer greatly helps in suppressing the thermo-mechanical stress, and thus the keep-out zone.

Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice

Silicon-lattice distortion in the 50- μm-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ~ 1000 MPa of tensile stress and ~ -200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.

High density Cu-TSVs and reliability issues

Reliability issues such as thermo-mechanical stress, extrusion of via metal, and die-cracking caused by high density Cu-TSVs in 3D-LSI Si die/wafer after wafer thinning and bonding have been systematically investigated respectively using micro-Raman spectroscopy, laser microscopy, and optical microscopy techniques. It is inferred that (i) for the TSV pitch value of less than twice the TSV-width, the remnant stress present in the Si at the TSV space region is turned to be only compressive, i.e. in the lateral direction, the compressive stress produced by the adjacent TSVs overlapped to each other; for the TSV pitch values of greater than two times the TSV-width, the compressive stress in the Si at the vicinity of TSV is followed by the tensile stress and beyond that it becomes stress free at the TSV space region; (ii) Irrespective of the TSV shape and size, the lateral extrusion of Cu occurs at the TSV space region. The lateral extrusion becomes prominent for the larger TSV size values and the higher bonding temperatures. The lateral extrusion is larger for the 20 μm-width TSV annealed at the higher temperature (~4 μm @ 400 °C) than for the TSV annealed at lower temperature (a maximum of only 1.5 μm @ 200 °C); (iii) Cracking of LSI die/wafer occurs at the periphery of the TSV array for very fine pitch values, and for larger pitch values cracking occurs in between TSVs.

Mechanical Characteristics of Thin Die/Wafers in Three-Dimensional Large-Scale Integrated Systems

A thickness value of less than 50 μm for die/wafers is a must meet criteria in 3-D large-scale silicon device integration, in order to reduce interconnect lengths and resistive-capacitive delays. The mechanical properties of such ultra-thin die/wafers, namely, Youngs modulus, hardness, etc., with respect to 1) different die thinning processes (chemical mechanical polishing, plasma etching, dry polishing, kai-dry polishing, poly grinding, ultra-poly grinding, #2000, etc.); 2) various wafer thicknesses (10, 20, 30, 40, 50, 100, and 200 μm); and 3) different wafer types (P/P+, P/P-, and wafers with internal-gettering layers) were investigated by using a nano-indenter. The mechanical characteristic data obtained for the thin die/wafers were well supported by their corresponding residual stress values (obtained by laser micro-Raman spectroscopy) and the crystal mis-orientation results (obtained via electron back-scatter diffraction). The chemically-mechanically polished ultrathin dies/wafers were found to be extremely good from the perspective of both mechanical strength and residual stress when compared to their counter parts fabricated by all other die thinning methods considered in this study.

Capacitance characteristics of low-k low-cost CVD grown polyimide liner for high-density Cu through-Si-via in three-dimensional LSI

Minimization of the parasitic capacitance arising from Cu–through-Si-vias (TSVs) has been rigorously considered in order to enhance the performances of three-dimensional (3D) LSIs. We have systematically investigated the role of chemical vapor deposited (CVD) polyimide (PI) liner in Cu-TSVs in reducing the TSV capacitance. It is confirmed that CVD grown PI greatly helps to reduce the TSV capacitance as compared to the conventional PECVD-SiO2 liner. In addition to that the presence of very small hysteresis and a negligible flat-band voltage shift along the voltage axis confirms the suitability of PI liner as dielectric in the Cu-TSVs, if it were operated below the bias voltages of ±20 V. In over all, the large reduction in capacitance along with the conformal deposition of PI in the TSVs having less than 3 µm-width with aspect ratios greater than 10 reveals that CVD grown PI has the potential application in the future 3D-LSIs with highly scaled TSV.

Characterization of Vapor Deposited Polyimides and Process Integration with the Polymeric Liner for Via-Last/Backside-Via Cu-TSV Formation

Abstract A vapor deposited polyimide (PI) as a TSV (through-Si via) dielectric liner is studied for 3D integration based on via-last/backside-via processes. In this work, Kapton-H is employed for a candidate of the PI TSV liner. The leak current (~ 1×10 A/cm) of the vapor deposited PI is low, and in addition, the PI liner shows lower thermal mechanical stress than a SiO2 liner deposited by plasma CVD with TEOS. The etching rates of the vapor deposited PI formed on the via top, sidewall, and bottom are approximately 1,300, 400, and 1,000 nm/min, respectively, suggesting that the vapor deposited PIs can be applied to TSV liners for via-last/backside-via 3D integration.

Improving the barrier ability of Ti in Cu through-silicon vias through vacuum annealing

Suppressing leak current and blocking Cu diffusion into active Si from Cu through-silicon vias (TSVs) are important requirements for enhancing three-dimensional (3D) LSI performance and reliability. We have proposed and confirmed a cost effective means of enhancing the barrier property of sputtered Ti in high-aspect-ratio Cu-TSVs by simple vacuum annealing at 400 °C for 20 min. The self-formed amorphous TiSi2 at the interface between dielectric SiO2 (along the TSV side-wall) and barrier Ti layer is found to play a positive role in improving the leak current characteristics. As-formed TiSix was partially converted into TiO2 and SiO2 during the vacuum annealing above 200 °C, and nearly vanished after annealing at 400 °C. The immense importance of 400 °C vacuum-annealing is not only in terms of the improvement in the barrier characteristics of the Ti layer, but also it is being a prerequisite for preventing Cu popup in 3D-LSI. Both the X-ray photoelectron spectroscopy (XPS) and current–voltage (I–V) data clearly reveal that this simple vacuum annealing of Cu-TSVs at 400 °C has tremendous potential for implementation in cost-effective via-last 3D integration.

Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSi x for via-last TSV technology

With in the process temperature limit of less than 400 °C for via last technology, a simple method to improve the barrier ability of Ti layer in through Si via (TSV) has been studied. After annealing the TSV structures in vacuum at temperatures up to 400 °C, we did observe a tremendous improvement in leak current characteristics for SiO2 dielectric. It was found that the self-formed TiSix at the interface between Cu and SiO2 during the sputter deposition of Ti barrier layer was converted into an amorphous TiOx and SiOx upon vacuum annealing. This simple vacuum annealing of Cu-TSVs is a promising approach for using Ti as barrier layer in via-last 3D-integration.