Yujie Ai

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the characterization and analysis of this unique one-dimensional nanowire-channel device with three-dimensional surrounding-gate from experiments and simulation, including carrier transport behavior, parasitic effects, noise characteristics, self-heating effect, variability and reliability, which can provide useful information for the GAA device hierarchical modeling and device/circuit co-design.

Experimental Demonstration of Current Mirrors Based on Silicon Nanowire Transistors for Inversion and Subthreshold Operations

In this brief, the silicon nanowire transistor (SNWT)-based circuits of current mirrors (NWCMs) have been successfully fabricated for the first time. The key figures of merit of current mirrors (CMs) are experimentally studied, including output voltage coefficient (OVC), output resistance, and dc matching error ε. The experimental results indicate that, due to the unique quasi-1-D transport properties of the SNWTs, NWCMs exhibit superior performance than planar metal-oxide-semiconductor-field-effect-transistor-based CMs (PCMs) in the inversion operation region. Furthermore, NWCMs operating in the subthreshold region shows even better performance than PCMs. With the inherent advantages of the gate-all-around structure, the SNWT is very promising for analog and mixed-signal integrated circuits and particularly has its unique potential at subthreshold operation for low-power applications.

New understanding of the statistics of random telegraph noise in Si nanowire transistors - the role of quantum confinement and non-stationary effects

In this paper, the random telegraph noise (RTN) statistics in silicon nanowire transistors (SNWTs) are comprehensively studied. The capture/emission time constants and probabilities are found to be strongly impacted by the quantum confinement in SNWTs, which cannot be fully explained by classical RTN theory. A full quantum RTN model for SNWTs is proposed for fundamental understanding of the experiments. The characteristics of non-stationary RTN in SNWTs under high-field biases are studied for the first time, based on the developed statistical trap-response (STR) characterization method. The trap capture probability is found to be much different from that of the quasi-stationary RTN, leading to large errors in circuit aging prediction if using traditional RTN distributions. These new understandings are critical for robust SNWT circuit design against RTN.

Two-Dimensional Self-Limiting Wet Oxidation of Silicon Nanowires: Experiments and Modeling

In this paper, a CMOS compatible silicon nanowire (Si NW) fabrication method on bulk silicon substrate is carried out using the self-limiting oxidation (SLO) to accurately control its size and cross-sectional shape. A predictive model for the 2-D SLO of Si NWs is presented. In this model, both the reduced reaction rate and diffusivity result in the oxidation rate degradation. The orientation dependence and the deformation of silicon core and oxide shell are further discussed here. The modeling results show good agreement with the experimental data within a wide range of oxidation temperatures, oxidation time, and various initial silicon core sizes. This model provides useful process design guidelines for Si nanostructures, especially in controlling the final diameter and cross-sectional shape of Si NWs from the top-down approach.

New observations of suppressed randomization in LER/LWR of Si nanowire transistors: Experiments and mechanism analysis

In this paper, the nanowire (NW) line-edge/width roughness (LER/LWR) effects in Si nanowire transistors (SNWTs) are investigated by both experiments and theoretical analysis. New LER/LWR characteristics are first observed in SNWTs, which exhibits suppressed randomization and enhanced systematic variation, rather than pure random LER/LWR in planar and FinFET devices. An improved characterization method is proposed to distinguish the random and systematic variation components in NW LER/LWR. For the first time, the effects of the key fabrication process on the NW LWR are studied in detail, including impacts of different oxidation temperature, NW channel orientations, and patterning techniques (hardmask trimming, spacer define and E-beam lithography). The results indicate that the spacer define method combined with self-limiting oxidation is beneficial for SNWTs. The mechanism of reducing the random variation in NW LER/LWR is analyzed, considering 2-D stress-retarded curvature-dependent oxidation. Taken into account the variation of quantum confined carrier profile, a physical device model is also developed, providing some guidelines for LER/LWR-hardening design of SNWTs.

Top-down fabrication of vertical silicon nano-rings based on Poisson diffraction

Vertical Si nano-rings with a uniform thickness of about 100 nm have been fabricated by conventional optical photolithography with a low cost based on Poisson diffraction. Moreover, the roughness of the Si nano-rings can be effectively reduced by sacrificial oxidation. In order to increase the density of the nano-rings, coaxial twin Si nano-rings have been fabricated by the Poisson diffraction method combined with the spacer technique. The thickness of both the inner and outer Si nano-rings is about 60 nm, and the gap between the twin nano-rings is about 100 nm.

Variability investigation of gate-all-around silicon nanowire transistors from top-down approach

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices. This paper discusses the process impact on nanowire LER/LWR, as well as the impact of 2D nanowire LER on performance variation and degradation. And it is found that SNWTs, which is immune to channel RDF(random dopant fluctuation), exhibit SDE-RDF which is enhanced by diameter-dependent annealing. In addition, the different impacts of the experimentally extracted variation sources in SNWTs on the threshold voltage and on current flucturation is discussed, as well as the variability impact on SNWT based SRAM cells compared with planar SRAM cells.

Self-heating effect and characteristic variability of gate-all-around silicon nanowire transistors for highly-scaled CMOS technology (invited)

This paper discusses self-heating effect and variability behavior of GAA SNWTs. Due to the 1-D nature of nanowire and increased phononboundary scattering in GAA structure, the selfheating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally extracted and studied in detail. And the impacts of nanowire LER, the diameter-dependent annealing enhanced nanowire This paper discusses self-heating effect and variability behavior of GAA SNWTs. Due to the 1-D nature of nanowire and increased phononboundary scattering in GAA structure, the selfheating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally extracted and studied in detail. And the impacts of nanowire LER, the diameter-dependent annealing enhanced nanowire

Investigations on the Impact of the Parasitic Bottom Transistor in Gate-All-Around Silicon Nanowire SONOS Memory Cells Fabricated on Bulk Si Substrate

Gate-all-around (GAA) Si nanowire SONOS memory cells (SNWMs) have been fabricated on Si substrate using fully epi-free compatible CMOS technology. A parasitic bottom SONOS memory (PBM) was formed when the SNWM was fabricated on bulk Si substrate. The impact of the PBM on the performance of the SNWM is investigated in this paper. The PBM shows a slower program speed, a faster erase speed, and worse retention characteristics than the SNWM. Therefore, the PBM severely degrades the performance of the SNWM due to its slower program speed and worse retention characteristics, and should be carefully controlled for the SNWM based on bulk Si substrate.