Jifa Hao

The impact of trench geometry and processing on the performance and reliability of low voltage power UMOSFETs

We report on the performance and reliability of n-channel U-shaped trench-gate metal-oxide-Si field-effect transistors (n-UMOSFETs). Damage induced on the trench sidewalls from the reactive ion etching of the trench is concealed by post-etch cleaning as witnessed by the independence of the effective electron mobility in the channel of the trench geometry. However, charge pumping measurements coupled with electrical stressing of the gate oxide in the Fowler-Nordheim (FN) regime, have shown that the oxide edge adjacent to the drain and the oxide/silicon interface therein are the most susceptible regions to damage in the n-UMOSFET. Using scanning electron microscopy, this is shown to result from gate-oxide growth nonuniformity that is more pronounced at the trench bottom corners where the oxide tends to be thinnest. We also report on n-UMOSFET performance and hot electron stress reliability as functions of the p-well doping.

The effects of channel boron-doping on the performance and hot electron reliability of N-channel trench UMOSFETs

Abstract We report on the effects of channel doping on the performance and hot electron stress (HES) reliability of U-shaped trench gate metal-oxide–silicon field-effect transistors (UMOSFETs). The boron-doped n-channel UMOSFETs are examined using transistor parameters and charge pumping current measurements. It is shown that increasing boron doping of the channel degrades UMOSFETs performance via decreasing the effective electron mobility in the channel and increasing the electron drift resistance in the drain region of the device. It is shown that increasing the boron doping of the channel does not increase interface trap density, which is a major cause for mobility reduction in MOSFETs: instead, ionized impurity scattering in the channel as well as the electric field transverse to the device channel, both of enhanced by doping, are argued to primarily cause the observed degradation in the electron mobility. The UMOSFETs response to HES is observed to be dependent on the doping level of the channel and is discussed in terms of the hot electron energy and its influence by channel doping.

Modeling microstructure effects on electromigration in lead-free solder joints

This paper studies the microstructure effects on electromigration in lead-free solder joints in wafer level chip scale package (WL-CSP). It is an extension of an earlier isotropic model [1]. The three dimensional finite element model for solder joints is developed and analyzed in ANSYS®. A sub-modeling technique combined with an indirect coupled electrical-thermal-mechanical analysis is utilized to obtain more accurate simulation results in solder bumps. Four representative microstructures of the solder bumps are modeled and anisotropic elastic, thermal and diffusion property data are used. The results obtained from the four representative microstructures are compared with each other. The microstructure effects on electromigration are drawn from the plots of the atomic flux divergence (AFD) and the time to failure (TTF) with respect to microstructure parameters.

High temperature bias-stress-induced instability in power trench-gated MOSFETs

Abstract We report on the high-temperature reverse-bias (HTRB) stress reliability of trench-gated n-channel metal-oxide-silicon field-effect transistors (n-UMOSFETs). The degradation induced by the HTRB is examined using changes in transistor parameters, optical microscopy, and scanning electron microscopy. The HTRB causes degradations in the threshold voltage and drain leakage of the n-UMOSFET and these degradations are particularly large when the stress is applied in a humid ambient. The observations were interpreted in terms of water molecule diffusion into the gate oxide through passivation cracks in the edge termination of the n-UMOSFET during HTRB in a humid ambient. The water molecules catalyze proton (H + ) generation through electric-field assisted interactions and hole injection into the gate oxide at the bottom of the trench. Also, H + is observed to be very stable in the gate oxide and to migrate between the gate-oxide and oxide–Si interfaces driven by an applied gate-voltage. It is proposed that the employed HTRB configuration and level give rise to negative-bias temperature instability (NBTI) in a parasitic p-channel MOSFET structure occurring in the trench base of the n-UMOSFET, and that NBTI is a serious reliability concern in power UMOSFETs subjected to stress in a moist ambient.

Observation of negative bias temperature instabilities in parasitic p-channel MOSFETs occurring during high-temperature reverse-bias stressing of trench-gated n-channel MOSFETs

High-temperature reverse-bias (HTRB) stress in a dry or a humid ambient is applied to power n-channel U-shaped trench-gated MOSFET (UMOSFETs). The HTRB is shown to induce negative-bias temperature instabilities (NBTI) in a parasitic p-channel MOSFET occurring in the n-channel UMOSFET during the stress. The manifestations of the NBTI were gate-controlled shifts in the threshold voltage, Vth, and in the drain-to-source leakage current, IDSS, following only humid HTRB stress. SEM inspection of UMOSFETs deprocessed to passivation showed the presence of passivation cracks on the edge termination only in devices that degraded with the HTRB stressing. Our results lead us to conclude that only humid HTRB/NBTI stress causes changes in Vth and IDDS. During the stress water or hydrogen species diffuse into the gate oxide through passivation cracks at the edge of the UMOSFET, and react with the gate oxide in the presence of holes and release protons. The protons are not confined to the gate oxide at the trench-bottom and are able to migrate up the oxide on the trench sidewalls.

Electromigration Induced Stress in Lead-Free Solder Joints

A finite element-based simulation approach is used to predict stress evolution resulting from electromigration-induced diffusion. A diffusion-mechanical coupled model is developed where the electromigration and stress-induced diffusion is coupled to the mechanical equilibrium with an introduction of the electromigration induced inelastic strain. A crystal plasticity constitutive model is developed to capture the plastic anisotropy of Sn. The problem is solved using a staggered approach at each time step. Simulations are conducted on a simplified geometry of a single crystal Sn cylinder and stress evolution is obtained with different current densities and Sn crystal orientations.

Crystal plasticity finite element analysis of electromigration-induced deformation behavior in lead-free solder joints

The elastic and plastic anisotropy of β-Sn has an important effect on the stress state, and hence the electromigration induced degradation in Sn-based solder joints. A crystal plasticity model is developed to capture this effect. Calibration of this model is done by using the available literature data. Future refinement of the slip parameters is needed to optimize the model. The model is implemented in a finite element framework and is used to simulate the response of single crystal β-Sn to electromigration induced strains. This work can be used as a basis for future development of coupled models of electromigration and stress induced degradation in Sn-based solders.

Self heating effect on hot carrier degradation characteristic in high voltage n-channel LDMOS

This paper reports on self heating caused by hot-carrier (HC) stress in packaged thick gate oxide HV LDMOS devices, and how self heating significantly affects HC degradation characteristics. The time delay between the removal of the HC stress and the parameter measurement significantly after each stress cycle significantly affected the measured HC Idlin/Rdson degradation. For a longer delay time, lower Idlin degradation was observed. The difference, or recovery, of degradation with longer delay time was mainly due to the self heating effect. The Idlin degradation from self heating effect seems to be more than from the HC effect in packaged HV LNDMOS. Based on the data, some methods are proposed to eliminate the self heating effect, and to separate the self heating and local HC injection effect.

Electromigration prediction and test for 0.18μm power technology in wafer level reliability

This paper investigates the electromigration prediction and test for a 0.18μm power technology in a wafer level reliability interconnect structure. The driving force for electromigration induced failure considered here includes the electron wind force, stress gradients, temperature gradients, as well as the atomic density gradient. Both the electromigration prediction and test for chemical-mechanical planarization (CMP) and non-CMP power devices are investigated. Parameters of different barrier metal thicknesses are studied. The simulation also gives the effect comparison with and without consideration of the atomic density gradient. The results showed that the predicted electromigration mean time to failure (MTTF) are well correlated with the experimental test data.

Characterization of gate oxide degradation mechanisms in trench-gated power MOSFETs using the charge-pumping technique

The high-electric-field stress reliability of trench-gated power MOSFETS has been characterized using high-resolution scanning electron microscopy, transistor parameter, and charge-pumping measurements. Degradation due to electrical stress was observed to be in the form of positive charge accumulation at the drain edge of the channel. This results in an effective shortening of the electrical channel length. Oxide thinning at the trench corners together with sidewall roughness caused by the trench etch are suggested as the mechanisms responsible for this observation. Design approaches to alleviate this effect are demonstrated.