S.A. Suliman

Modified three terminal charge pumping technique applied to vertical transistor structures

Vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) have evolved into dominant members in the power transistor family. Reliability issues continue to be a major concern, as economic requirements drive towards miniaturization, and higher power ratings for these devices. The charge pumping method offers a simple, direct and powerful way of assessing interface damage for planar structures. Absence of an independent substrate contact in the vertical power structure implies that conventional charge pumping, which requires a substrate contact as well as three additional contacts to the remaining terminals of the MOSFETs, cannot be applied directly to these devices. In this article, we propose an adaptation of the charge pumping technique that enables its application to three terminal devices, in general. The modified form of charge pumping was applied to assess effects of Fowler–Nordheim stressing on production level U-shaped trench-gated MOSFETs. A good correlation between transfer characteri...

The impact of trench geometry and processing on the performance and reliability of low voltage power UMOSFETs

We report on the performance and reliability of n-channel U-shaped trench-gate metal-oxide-Si field-effect transistors (n-UMOSFETs). Damage induced on the trench sidewalls from the reactive ion etching of the trench is concealed by post-etch cleaning as witnessed by the independence of the effective electron mobility in the channel of the trench geometry. However, charge pumping measurements coupled with electrical stressing of the gate oxide in the Fowler-Nordheim (FN) regime, have shown that the oxide edge adjacent to the drain and the oxide/silicon interface therein are the most susceptible regions to damage in the n-UMOSFET. Using scanning electron microscopy, this is shown to result from gate-oxide growth nonuniformity that is more pronounced at the trench bottom corners where the oxide tends to be thinnest. We also report on n-UMOSFET performance and hot electron stress reliability as functions of the p-well doping.

The dependence of UMOSFET characteristics and reliability on geometry and processing

We have examined the impact of trench processing and trench and device cell geometries on the characteristics of a single n-channel U-shaped trench metal-oxide-silicon field-effect transistor (n-UMOSFET) and a device cell comprising several n-UMOSFETs. The geometrical parameters investigated included the trench depth and width, the trench cross-section and the device cell pitch. We have found out that the geometry does not affect the electron mobility in the channel; however, the effects of the geometry on the characteristics of the isolated device or device cell are manifested on the spreading resistance of the drain end. Trench processing, in the form of trench etching, trench cleaning and subsequent gate-oxide growth, is observed to primarily influence the n-UMOSFETs immunity to electrical stress, which is studied using charge pumping current and gate-oxide breakdown measurements. It is shown that the gate-oxide edge adjacent to the drain and the oxide/silicon interface overlapping the drain are the regions most susceptible to degradation by Fowler-Nordheim stress. These observations coupled with results from scanning electron microscopy suggest that the gate-oxide growth non-uniformity as well as its condition at the trench corners are the key factors in determining the n-UMOSFETs reliability.

The effects of channel boron-doping on the performance and hot electron reliability of N-channel trench UMOSFETs

Abstract We report on the effects of channel doping on the performance and hot electron stress (HES) reliability of U-shaped trench gate metal-oxide–silicon field-effect transistors (UMOSFETs). The boron-doped n-channel UMOSFETs are examined using transistor parameters and charge pumping current measurements. It is shown that increasing boron doping of the channel degrades UMOSFETs performance via decreasing the effective electron mobility in the channel and increasing the electron drift resistance in the drain region of the device. It is shown that increasing the boron doping of the channel does not increase interface trap density, which is a major cause for mobility reduction in MOSFETs: instead, ionized impurity scattering in the channel as well as the electric field transverse to the device channel, both of enhanced by doping, are argued to primarily cause the observed degradation in the electron mobility. The UMOSFETs response to HES is observed to be dependent on the doping level of the channel and is discussed in terms of the hot electron energy and its influence by channel doping.

Defect states in carbon and oxygen implanted p‐type silicon

The presence of electrically active defects in C+ and CO+ implanted boron‐doped silicon has been monitored using deep level transient spectroscopy and resistivity measurements. Activation energies of trapped carriers, implanted ion dependencies, and annealing behavior of these defects have been determined. The introduction of defects by annealing has been observed. A total of ten hole and electron traps are reported. Among these traps, a dominant hole trap 0.65 eV above the valence band, and an electron trap 0.53 eV below the conduction band, are tentatively ascribed to the silicon di‐interstitial and the carbon‐oxygen pair, respectively. Other traps detected in the samples have been correlated with multi‐oxygen‐ and carbon‐related complexes. Annealing at temperatures up to 400 °C gives rise to similar deep level transient spectroscopy spectra comprising the same traps in both C+ and CO+ implanted material. However , annealing at temperatures >500 °C produces defect states that are dependent on the implan...

On the propensity of guiding surface-plasmon-polariton waves by the back-contact of an amorphous silicon p-i-n solar cell

The effect of varying the n-layer on the propensity of guiding surface-plasmon-polariton (SPP) waves by the back-contact of a p-i-n solar cell was studied theoretically. The i-layer was assumed to consist of an a-SiGex:H homogeneous layer of bandgap energy 1.3 eV. To determine the SPP waves that can propagate at the metal/multilayer material interface, a canonical boundary-value problem comprising periodically repeated p-i-n semiconductor layers partnering a homogeneous metal was solved for four different n-layers. The canonical problem was formulated to predict both of the TM- and TE-polarized SPP waves that can be guided by the interface. It was found that the configurations that have an amorphous silicon layer partnering the metal have equivalent propensity for guiding TM- and TE-polarized SPP waves by the planar metal/multilayer material interface, although their phase speeds, e-folding distances, and localization are slightly altered. On the other hand, the configuration that has an aluminum zinc oxide partnering the metal has significantly reduced propensity for guiding TE-polarized SPP waves. To examine the excitability of the SPP waves predicted from the canonical problem, one of the considered configurations is incorporated in a practical grating-coupled configuration. Oblique incidence was assumed, and multiple SPP waves were successfully excited. The total absorptance of the p-i-n solar cell shows enhancement at the SPP wave excitation wavelengths.

High temperature bias-stress-induced instability in power trench-gated MOSFETs

Abstract We report on the high-temperature reverse-bias (HTRB) stress reliability of trench-gated n-channel metal-oxide-silicon field-effect transistors (n-UMOSFETs). The degradation induced by the HTRB is examined using changes in transistor parameters, optical microscopy, and scanning electron microscopy. The HTRB causes degradations in the threshold voltage and drain leakage of the n-UMOSFET and these degradations are particularly large when the stress is applied in a humid ambient. The observations were interpreted in terms of water molecule diffusion into the gate oxide through passivation cracks in the edge termination of the n-UMOSFET during HTRB in a humid ambient. The water molecules catalyze proton (H + ) generation through electric-field assisted interactions and hole injection into the gate oxide at the bottom of the trench. Also, H + is observed to be very stable in the gate oxide and to migrate between the gate-oxide and oxide–Si interfaces driven by an applied gate-voltage. It is proposed that the employed HTRB configuration and level give rise to negative-bias temperature instability (NBTI) in a parasitic p-channel MOSFET structure occurring in the trench base of the n-UMOSFET, and that NBTI is a serious reliability concern in power UMOSFETs subjected to stress in a moist ambient.

Growth and reliability of thick gate oxide in U-trench for power MOSFETs

Growth kinetics and reliability of thick gate oxides grown into 2 /spl mu/m deep trenches is investigated. The oxide thickness nonuniformities are observed at the bottom of the trench. It is postulated that thinning of the oxide at the bottom of the trench is a result of an insufficient supply of oxidizing species which nonuniformities are enhanced by 2D oxidation in the corners. The effect of 2D oxidation is more pronounced in narrow trenches. The reliability of trench oxides was found to be dependent on the oxidation temperature, trench geometry, and substrates conductivity type. No effect of temperature of oxidation and trench geometry on interface trap density was observed.

Electrical properties of the gate oxide and its interface with Si in U-shaped trench MOS capacitors: The impact of polycrystalline Si doping and oxide composition

Abstract We have examined boron penetration from heavily boron-doped p + -polycrystalline-Si gate into the gate dielectric/Si-sidewall interface and into bulk Si of U-shaped trench metal-oxide-Si capacitor. We have found that the inclusion of a thin nitride layer atop the thermal gate oxide inhibits boron penetration from the boron-doped p + -polycrystalline-Si gate into the dielectric/Si-sidewall interface and into bulk Si. The incorporation of the nitride layer on top of the thermal oxide to produce a two-layer gate dielectric, however, is observed to result in a significantly weaker dielectric, which breaks down at relatively low electric fields. This is the first time that degradation in breakdown qualities of thermal oxides in the presence of nitride layers is reported. Interface state bands are observed by deep level transient spectroscopy. These bands cover most of the Si bandgap and are of comparable concentrations in capacitors with different gate dielectric compositions (e.g., bare oxide, nitride-on-oxide or oxynitride) irrespective of the polycrystalline-Si gate doping (e.g., boron-doped p + or phosphorus-doped n + ). These energy bands are argued to be independent of gate dopant atoms as well as independent of nitrogen atoms coming from the oxynitride in the gate dielectric.

On the 0.34 eV hole trap in irradiated boron-doped silicon

Abstract A detailed deep level transient spectroscopy (DLTS) study has been carried out on a prominant hole trap at 0.34 eV above the valence band in irradiated p-type silicon. The boron concentration in the float zone and Czochralski-grown samples varied between 1012 and 1016 cm−3, and irradiations with 2.0 MeV electrons have been performed at nominal room temperature to total fluences of 1.0 × 1016 and 1.0 × 1017 e−/cm2. The introduction rate of the trap is strongly boron-dependent, while the oxygen content in the samples does not influence neither the trap production rate nor its observed annealing behaviour. In the light of these observations and other available data on this trap, a boron-carbon pair is here tentatively proposed as the defect identity. A previously unreported hole trap at 0.45 eV above the valence band has also been observed in this work in highly boron-doped material. The isothermal and isochronal annealing characteristics of both traps have been investigated up to 400°C.