Yinglei Ren

Switching voltage regulator noise coupling to connector signal pins through near field radiation

In a server system, the switching voltage regulator (VR) noise coupled to the IO pins of the adjacent memory riser connector through the open air above the base board, and the link performance was impacted by the coupling. A simulation flow was developed to reproduce this EMI phenomenon. The flow first used electromagnetic field solvers to extract the VR related power network and the VR-IO coupling network, and then the di/dt and dv/dt noise sources and the induced IO noise were solved in HSpice®. The simulation revealed the underlying coupling mechanism: The high frequency current loop formed by the power MOSFET, the VR power shapes, the snubber RC circuit at the bottom layer of the board, and the stitching via acted as a transmitting loop antenna, and the radiating field propagated through the air and was picked up by another loop (receiving antenna) formed by the riser connector pins. An effective mitigation method is to use bigger snubber resistor to damp this near field radiation. Both the coupling theory and the effectiveness of the mitigation method were proved by the measurements.

Inter-layer crosstalk management in differential dual-striplines

Dual-stripline is gaining popularity in computer designs to save printed circuit board (PCB) cost and achieve more compact form factor. A key concern in dual-stripline design is the inter-layer crosstalk (ILC). In this paper, differential dual-stripline crosstalk is investigated, and a complete design strategy is provided. In addition to the conventional crosstalk mitigation techniques, an innovative wiring technique is proposed to reduce ILC for parallel dual-striplines. The proposed routing strategy can effectively mitigate the impact of ILC, and, as a result, enable high-density PCB layout, achieve compact form factor, and save the bill of material (BOM) cost.

A new design flow to evaluate high-speed SerDes link performance with re-driver

Due to non-LTI behaviour of re-driver, simulation methodology and model format are still working in progress for continuous improvement on accuracy and efficiency to perform statistical analysis such as BER for high-speed serial IO links. In this paper, a measurement based methodology is proposed and introduced to provide a flow and methodology to evaluate re-driver link performance. The methodology is based on re-driver assessment board to obtain reference channel through measurement by meeting industry IO specifications. Channel Quality Comparison (CQC) is then introduced and used to evaluate risk level of the proposed design topology by benchmarking to the reference channels. Design engineers can use the flow and methodology introduced in this paper to evaluate link performance for their proposed topology in addition to using simulation. A design example on test platform for USB3 is reported to demonstrate the usage with measurement results.

Crosstalk analysis for dual stripline with parallel and angled routing

Dual stripline routing is more and more widely used in the modern high speed PCB design due to its cost advantage of reduced overall layer count. However, the major challenge of a successful dual stripline design is to handle the additional interferences introduced by the signals on adjacent layers. This paper studies the crosstalk effect of the dual stripline with both parallel and angled routing, and proposes design solutions to tackle the challenge. Analytical and empirical algorithms are proposed to estimate the crosstalk waveforms from multiple aggressors, which provide quick design risk assessment, and the waveform is well correlated to the 3D full wave EM simulation results.

Dual-striplines design optimizations for minimum crosstalk

Dual-stripline is widely used in the computer systems to save printed circuit board (PCB) cost and achieve more compact form factor. Many design parameters can affect the overall performance of the dual-striplines. In this paper, the optimization of the dual-stripline design is discussed in detail, such as stackup selection, component breakout, etc. Theory analysis as well as Three-Dimensional full-wave modelling results of the inter-layer crosstalk for both single-ended and differential dual-stripline are presented to understand the inter-layer crosstalk. Measurement data from a test board is used to correlate the modeling result. An end-to-end simulation flow is proposed to precisely evaluate the overall crosstalk and full-link performance of a design with dual-stripline.

VR noise analysis and reduction in printed circuit board designs

Noise caused by switching voltage regulator (VR noise) can have a big impact on system signal / power performance, leading to signal integrity (SI) / power integrity (PI) issues. This paper introduces systematic ways of reducing VR noise as well as VR noise analysis methods. And a real design case with VR noise issue is shared with simulation and measurement results.

Signal integrity performance degradation due to temperature variation in systems with re-drivers

Re-drivers are widely used in extending the solution space in high speed applications. However, recent lab data shows that the ambient temperature variation can lead to ~40mV degradation of the eye height at the receiver side on single re-driver system. In this paper, the authors will share key learnings of thermal impact on systems with both single re-driver and cascaded re-drivers. From these cases, the eye height is greatly reduced when temperature increases. This variation is due to resistance shifting of the output buffer, while most re-driver models do not account for it. An effective approach is applied to fine tune the equalization settings in the cascaded re-driver system. The learnings, together with the proposed approach, can help designers to design a robust, high performance, and cost-effective high speed link with re-drivers such as SAS-3, SATA-3, PCIe and USB, etc.

SI architecture optimized high speed serial design for PCB cost saving

As integrated circuit (IC) chips keep growing in size, I/O data rates and complexity, electrical margin left on printed circuit board (PCB) gets smaller. Mid-loss or even low-loss material may be needed in more cases to meet high speed (HS) signal routing length requests, which leads to cost-adder on PCB. This submission introduces analysis flow as well as practical methods targeting reducing PCB material cost through SI architecture optimization. Following the analysis flow, board designers can get better opportunity of using cheaper material without sacrificing performance.

Case learnings of power noise impact on SATA

With the increase of data rate, signal integrity (SI) becomes a bigger challenge for printed circuit board (PCB) designs. Power noise as well as signal loss, inter-symbol interference (ISI), crosstalk needs to be taken into account to ensure a good quality signal design. In this paper, a design case is shared where power noise greatly impacts SATA performance and leads to hard disk (HDD) disconnection. Noise source and noise coupling path are root-caused with simulation and measurement data. And learnings from this case is summarized for future attention.

Debugging and analysis of a new noise coupling mechanism in computer system

Modern memory system is running at higher data rates with growing complexity, which makes debugging memory related system failure increasingly challenging. In this paper, we report a new memory failure mechanism due to unexpected crosstalk and resonant effect. An innovative full channel modelling & simulation methodology is proposed, which utilize both the time domain and frequency domain analysis to identify the problem, and then precisely predict the failure pattern, as well as the maximum noise level. The analysis also leads to an effective low cost solution, which is further verified by lab measurement. Design guidance for future products is also discussed.