Joong-Sik Kih

A low cost high performance register-controlled digital DLL for 1 Gbps/spl times/32 DDR SDRAM

A low cost high performance register-controlled digital delay-locked loop (DLL) that has novel resolution-enhancing structure with inherent duty cycle correction capability was developed for 1 Gbps/spl times/32 DDR SDRAM. Experimental results in a 0.13 /spl mu/m 4 M/spl times/32 DDR SDRAM show <25 ps peak-to-peak jitter with quiet supply, </spl plusmn/2% duty correction from external duty error of /spl plusmn/7%, <150 cycle lock-time, 24 mW at 1.8 V/400 MHz, 60 mW at 2.5 V/500 MHz, and a wide locking range from 66 MHz to over 500 MHz.

A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM

A new low power high performance register-controlled digital delay locked loop (LPRCDLL) is presented. The circuit has fine delay compensation ability, fast delay compensation according to external voltage variation, and inherent duty correction. The digital DLL used for 2Gbps 8M times 32 GDDR3 SDRAM is fabricated using a 0.10mum technology. Experimental results show less than plusmn1% duty correction from external duty error of plusmn5%, less than 400 cycle locking time, 1GHz operation frequency at 1.5V, 38mW at 1.5V/1GHz, and a wide locking range from 250MHz to 1GHz

A low power and highly reliable 400Mbps mobile DDR SDRAM with on-chip distributed ECC

512 Mb Mobile SDRAM with on-chip error-correction code (ECC), which supports either single or double data rate and operates on a 1.8 V power supply, is developed. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty. The ratio of ECC area increase compared with the conventional mobile DRAM is 15%, and the fast comparing circuits of built-in Hamming code technique check 12 cell data simultaneously and satisfy the specification of 400Mbps DDR SDRAM. The self refresh period at standby state shows about 6 times increase reducing the self refresh current to be less than 100uA at 85degC. The newly adopted DCCS in the ECC, which is resistant from the clustered failures, and the concurrent row redundancy produce a synergistic fault-tolerance effect. The reliability could be 106 times higher by the ECC than that of the conventional DRAM.

Crosstalk Cancellation of DDR3 Memory Channel for over 1600 Mbps Data Rate

In this paper, we propose crosstalk cancellation methodology for high speed DDR3 memory channel whose data rate is 1600 Mbps or faster. In DDR3, DQ signal still adopts microstrip line in the motherboard in order to achieve low cost. The propagation velocity of even-mode is different from that of odd-mode in the microstrip line, which results in skew among DQs and between DQ and data strobe (DQS) as well. This crosstalk reduces timing margin a lot and it is not endurable at the high data rate. The proposed method successfully suppresses the crosstalk and it is cost effective compared with using stripline for DQ and DQS in the motherboard.

A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

A new low power, low cost and high performance register-controlled digital delay locked loop with wide locking range is presented. The DLL has dual loops with single replica block, duty cycle correction enhance controller (DCCEC), smart power down controller (SPDC) for reducing the standby current during power down, and locking range doubler for wide locking range. The digital DLL used for 3 Gbps 512 Mb GDDR3 SDRAM is fabricated using an 80 nm DRAM Process. Experimental results show less than plusmn1% duty correction from external duty error of plusmn5%, less than 400 cycle locking time, 1.5 GHz operation frequency at 1.9 V, and a wide locking range from 50 MHz to 1.5 GHz.

Analysis of simultaneous switching noise by short-circuit current in CMOS-single ended driver

In this paper, we divided the switching current of output driver for single ended voltage mode signaling into two parts according to current flowing path. They are the direct current path and the channel current path, respectively. The impedance of the each current path is derived based on the analytical model. The current flowing through two current paths is calculated by using /spl alpha/-power model. From the impedance and current through driver, new expressions to estimate SSN in the CMOS voltage mode driver are derived. The derived expressions have a good agreement with HSPICE simulation results.

Digitally controlled phase locked loop with tracking analog-to-digital converter

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter - the key building blocks of digital PLL (DPLL), there is no need for the trade-off between jitter, power consumption and silicon area. The DCPLL was implemented in a 0.18mum CMOS process and the active area is 0.35 mm2. The DCPLL consumes 59mW during the normal operation and 984muW during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps rms jitter

Impact of package inductance and DQ driver strength on the 3 rd harmonic EMI from DRAM

This paper describes the impact of DRAM-caused power noise (especially simultaneous switching output noise) in DDR2 667 system. The power noise is regulated by adjusting the package inductance of power delivery nets, DQ driver strength, and the power supply voltage. The package inductances of core power delivery net (VDD/VSS) and the DQ power delivery net (VDDQ/ VSSQ) are controlled by adjusting the number of solder balls on package. Also, the DQ power noise is controlled by adjusting DQ driver strength. The power supply level adjusts to control both core and DQ power noises. In summary, DRAM power noise is closely related to the radiated emission, and DRAM power noise should be properly controlled to reduce EMI in digital system.

A DUAL-GATE CELL (DGC) FeRAM WITH NDRO AND RANDOM ACCESS SCHEME FOR NANOSCALE AND TERABIT NON-VOLATILE MEMORY

ABSTRACT This paper proposes a new dual-gate cell (DGC) FeRAM. The dual-gate cell is composed with MFSFET and MOSFET faced in parallel with common drain, source and float channel. The gates of the dual-gate cell are controlled by wordline and bottom wordline, respectively. A multitude of the dual-gate cells are arrayed in serial connection for unit array scheme. The WL_1 to WL_m of MFSFET are not biased for sensing operation in read mode, thus there are no degradation and disturbance to the cell retention data in read access. The write cycle composed with two sub-write cycles of data ‘1’ preserve or data ‘0’ write cycle after the first sub-write cycle of data ‘1’ write to all active cells. The data ‘1’ is preserved by the same voltage polarity between WL_1 and channel voltage of the MFSFET. The random access operation is possible in both read and write mode with non-destructive read out (NDRO).

Analysis of characteristics of transmission line with two reference planes through high-frequency measurements

A discontinuity of channel severely affects a signal quality on the high speed systems. The more the routing of signal lines is complicated, the reference changing happens frequently. This reference crossing brings about the sudden change of signal line impedance and the reflection from this fact distorts the transfer signal. In this paper, the reference crossing effects are analyzed from the circuit modeling.