Jin-Il Lee

Scalable High-Performance Phase-Change Memory Employing CVD GeBiTe

We first present chemical-vapor-deposited GeBiTe (CVD GBT) in a confined cell for high-performance phase-change random access memory (PRAM). Due to the fast crystallization of GBT, we were able to reduce the speed to less than 26 ns while maintaining endurance characteristics up to 109 cycles. Our results indicate that the scalable PRAM device enabling the use of PRAM in dynamic RAM and storage class memory applications can be realized using CVD GBT.

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions. Consequently, the memory bandwidth requirement has also been increasing, requiring a next-generation mobile DRAM standard. In this paper, we present a power-efficient LPDDR4 SDRAM operating at 3.2Gb/s/pin. Our LPDDR4 DRAM offers 2× bandwidth with improved power efficiency over LPDDR3 SDRAMs, due to the 2-channel architecture and low-voltage-swing terminated logic (LVSTL) [1]. Moreover, the supply voltage is further reduced to 1.0V in this work, 0.1V lower than the LPDDR4 standard, for extra power saving.

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time interleaved latency and IO control circuits enable 1.0 V operation at target speed. To reach 3.2 Gbps with improved power efficiency over conventional mobile DRAMs, the following IO features are introduced: Low voltage swing terminated logic drivers with VOH level calibration and periodic ZQ calibration, unmatched DQ/DQS scheme and DQS oscillator for DQS tree delay tracking. This chip is fabricated in 25 nm DRAM process on 88.1 mm 2 die area.

Improvement of Contact Resistance between Ru Electrode and TiN Barrier in Ru/Crystalline-Ta2O5/Ru Capacitor for 50 nm Dynamic Random Access Memory

The contact resistance (RC) between a Ru electrode and a TiN plug in a crystalline Ta2O5 capacitor using Ru electrodes was evaluated. The TiN plug was oxidized in TiOx to increase the RC to failure. Two origins of oxygen are determined by Auger electron spectroscopy (AES) analysis, namely, the seed step of Ru deposition and the initial step of Ta2O5 deposition. During Ta2O5 crystallization annealing at 700°C, the oxygen molecules from Ru diffused into the TiN plug, forming TiOx. Ru films with Ti exhibited a decreased RC below 1 kΩ/contact and an increased leakage current of a Ru/Ta2O5/Ru capacitor according to the applied voltage, compared with Ru films without Ti. The atomic layer deposition (ALD) Ru process including a H2 plasma treatment decreased the RC to 2.5 kΩ/contact on average. The fabrication scheme for the crystalline Ta2O5 capacitor using the Ru electrode for reducing RC between the Ru storage node and the TiN plug was proposed.

A robust alternative for the DRAM capacitor of 50 nm generation

As a new alternative for the DRAM capacitor of 50 nm generation, Ru/Insulator/TiN (RIT) capacitor with the lowest Toxeq of 0.85 nm has been successfully developed for the first time. TiO/sub 2//HfO/sub 2/ and Ta/sub 2/O/sub 5//HfO/sub 2/ double-layers were used as dielectric materials. After full integration into 512 Mbits DRAM device, the RIT capacitor showed good electrical properties and thermal stability up to 550/spl deg/C and its time-dependent-dielectric-breakdown behavior sufficiently satisfied 10-year lifetime within a DRAM operation voltage.

A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

A 7Gb/s single ended transceiver with low jitter and ISI is implemented in 40nm DRAM process. DRAM optimized LC PLL achieves inductor Q of 3.86 and results in random jitter of 670fs rms. A clock tree regulator with closed loop replica path reduces low as well as high frequency noise. RX 2-tap hybrid DFE combining sampling and integration methods reduces power and area by 37% and 24%, compared to the integrating DFE. Moreover, on-chip de-emphasis circuit in TX multiplexer reduces ISI of both on and off chip.