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Dive into the research topics where Sung-Lae Cho is active.

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Featured researches published by Sung-Lae Cho.


symposium on vlsi technology | 2010

High performance PRAM cell scalable to sub-20nm technology with below 4F2 cell size, extendable to DRAM applications

Ik-Soo Kim; Sung-Lae Cho; Dong-Hyun Im; Eun-ju Cho; D. H. Kim; Gyuhwan Oh; Dong-ho Ahn; Su-Jin Park; Seo-Woo Nam; June Moon; Chilhee Chung

A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F2. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation below 30nsec. The excellent writing endurance performance was predicted to maintain up to 6.5E15cycles by reset program energy acceleration. Its data retention was 4.5 years at 85°C which is enough for DRAM application.


IEEE Electron Device Letters | 2011

Scalable High-Performance Phase-Change Memory Employing CVD GeBiTe

Jin-Il Lee; Sung-Lae Cho; Dong-ho Ahn; Man-sug Kang; Seok-Woo Nam; Ho-Kyu Kang; Chilhee Chung

We first present chemical-vapor-deposited GeBiTe (CVD GBT) in a confined cell for high-performance phase-change random access memory (PRAM). Due to the fast crystallization of GBT, we were able to reduce the speed to less than 26 ns while maintaining endurance characteristics up to 109 cycles. Our results indicate that the scalable PRAM device enabling the use of PRAM in dynamic RAM and storage class memory applications can be realized using CVD GBT.


Journal of Applied Physics | 2015

Reduction of RESET current in phase change memory devices by carbon doping in GeSbTe films

J.H. Park; Seong-Oh Kim; J. Kim; Zhenhua Wu; Sung-Lae Cho; Dong-ho Ahn; D. H. Ahn; Jaeho Lee; S. U. Nam; D.-H. Ko

Phase Change Memory (PCM) has been proposed for use as a substitute for flash memory to satisfy the huge demands for high performance and reliability that promise to come in the next generation. In spite of its high scalability, reliability, and simple structure, high writing current, e.g., RESET current, has been a significant obstacle to achieving a high density in storage applications and the low power consumption required for use in mobile applications. We report herein on an attempt to determine the level of carbon incorporated into a GeSbTe (GST) film that is needed to reduce the RESET current of PCM devices. The crystal structure of the film was transformed into an amorphous phase by carbon doping, the stability of which was enhanced with increasing carbon content. This was verified by the small grain size and large band gap that are typically associated with carbon. The increased level of C-Ge covalent bonding is responsible for these enhancements. Thus, the resistance of the carbon doped Ge2Sb2Te...


Japanese Journal of Applied Physics | 2002

Integration of ferroelectric random access memory devices with Ir/IrO2/Pb(ZrxTi1-x)O3/Ir capacitors formed by metalorganic chemical vapor deposition-grown Pb(ZrxTi1-x)O3

Moon-Sook Lee; Kun-Sang Park; Sang-don Nam; Kyu-Mann Lee; Jung-Suk Seo; Suk-ho Joo; Sang-Woo Lee; Yong-Tak Lee; Hyeong-Geun An; Hyoung-joon Kim; Sung-Lae Cho; Yoon-ho Son; Young-Dae Kim; Yong-Joo Jung; Jang-Eun Heo; Soonoh Park; U-In Chung; Joo-Tae Moon

Metal organic chemical vapor deposition (MOCVD) of Pb(ZrxTi1-x)O3 (PZT) and its capacitor module process were established for ferroelectric memory device integration. The 130 nm-thick PZT films were deposited on Ir layers at 530°C or 550°C. The remnant polarization of the Ir/IrO2/PZT/Ir capacitors is in the range of 15 to 21 µC/cm2, and their leakage current is 10-5 A/cm2 at 2.5 V without additional annealing. The degradation in their switching endurance is less than 5% after 1010 cycles, indicating that the interfaces formed between the PZT and Ir layers can be optimized to improve their fatigue properties. To evaluate the capacitors on the devices, the conventional backend process was performed after encapsulating the capacitors with AlOx/TiOx layers located on the poly-Si plug. High charge separation and fully functional bit activities were obtained, demonstrating that this MOCVD-PZT process is a reliable integration scheme for high-density ferroelectric memory devices.


Integrated Ferroelectrics | 2002

Novel PZT Capacitor Technology for 32Mb and Beyond FRAM Device Using PbTiO 3 Seeding Layer

Kwang-Hyun Lee; Kyung-ho Park; Seungki Nam; Soo-Geun Lee; Suk-ho Joo; J. S. Seo; Young-dae Kim; Sung-Lae Cho; Yong-Hoon Son; H. G. An; Hee-seok Kim; Y. J. Chung; Jinseong Heo; Moon-Sook Lee; S.O. Park; U-In Chung; Joo Tae Moon

Effects of the PbTiO 3 (PTO) seeding layer on lowering the PZT crystallization temperature and reducing the capacitor stack height, especially PZT thin film, were systematically investigated. For these purposes, PZT film was modified by using the PTO seeding layer. By using the PTO seeding layer; the crystallization temperature of the PZT film was successfully lowered to 550C. And remanant polarization of PTO-used 100nm thick PZT capacitors measured at 3V was approximately 23 w C/cm 2 , that is 30% higher than that of the PTO-unused PZT capacitors. XRD analysis indicated that the use of the PTO seeding layer remarkably increased the relative intensity of (111) orientation. XRF studies showed that the atomic concentration ratio of Ti-to-Zr was increased by using PTO seeding layers. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Finally, we successfully developed a capacitor stack height of below 400nm, which was composed of Ir/IrO 2 /PZT/Pt/IrO 2 . Furthemore, by lowering the PZT crystallization temperature, small (600 z /contact) and stable contact resistance in a very small size of BC could be obtained.


Ferroelectrics | 2004

Novel PZT capacitor technology for high density FRAM device with 0.18 μm D/R

Kwang-Hyun Lee; Kyung-ho Park; Seungki Nam; Byoung-Jae Bae; Ji-Eun Lim; Moon-Sook Lee; Suk-ho Joo; Sung-Lae Cho; Su-Jin Park; U-In Chung; Joo Tae Moon

Novel capacitor technologies for high density FRAM device with 0.18 μm D/R (design-rule) have been researched and developed. In order to realize the high-density FRAM device with 0.18 μm D/R, the PZT film was modified by changing Zr/Ti composition and by using PTO seeding layer. Therefore, the crystallization temperature of the PZT film could be successfully lowered to 550°C. The remnant polarization of PTO-used 100 nm thick PZT capacitors measured at 2.7 V was approximately 24 μC/cm 2 , that is 30% higher than that of the PTO-unused PZT capacitors. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Furthermore, by lowering the PZT crystallization temperature and by applying robust TiAlN oxidation barrier, low (300 Ω/contact) and stable contact resistance in a very small size of BC could be obtained. Finally, we successfully developed a capacitor stack height of 270 nm. The capacitor size was 0.26 × 0.44 μm2 and remnant polarization measured at 2.7 V was approximately 11 μC/cm2.


AIP Advances | 2015

Improvement of reliability and speed of phase change memory devices with N7.9(Ge46.9Bi7.2Te45.9) films

J.H. Park; Seong-Oh Kim; J. Kim; D.-H. Ko; Zhe Wu; Sung-Lae Cho; Dong-ho Ahn; D. H. Ahn; J. M. Lee; Seo-Woo Nam

In this study, we propose a nitrogen-incorporated GeBiTe ternary phase of N7.9(Ge46.9Bi7.2Te45.9) as a phase change material for reliable PCM (Phase Change Memory) with high speed operation. We found that the N7.9(Ge46.9Bi7.2Te45.9) film shows the resistance value of 40 kΩ after annealing at 440oC for 10 minutes, which is much higher than the value of 3.4 kΩ in the case of conventional N7.0(Ge22.0Sb22.0Te56.0) films. A set operation time of 14 nsec was achieved in the devices due to the increased probability of the nucleation by the addition of the elemental Bi. The long data retention time of 10 years at 85oC on the base of 1% failure was obtained as the result of higher activation energy of 2.52 eV for the crystallization compared to the case of N7.0(Ge22.0Sb22.0Te56.0) film, in which the activation energy is 2.1 eV. In addition, a reset current reduction of 27% and longer cycles of endurance as much as 2 order of magnitude compared to the case of N7.0(Ge22.0Sb22.0Te56.0) were observed at a set operatio...


Archive | 2005

Methods for fabricating memory devices using sacrificial layers and memory devices fabricated by same

Suk-Hun Choi; Yoon-ho Son; Sung-Lae Cho; Joon-Sang Park


Archive | 2004

Methods for forming small features in microelectronic devices using sacrificial layers and structures fabricated by same

Suk-Hun Choi; Yoon-ho Son; Sung-Lae Cho; Joon-Sang Park


Archive | 2006

Method of forming a phase changeable material layer, a method of manufacturing a phase changeable memory unit, and a method of manufacturing a phase changeable semiconductor memory device

Jin-Il Lee; Choong-Man Lee; Sung-Lae Cho; Young-Lim Park

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Do-Hyung Kim

Pukyong National University

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