Byoung-Jae Bae

One-Dimensional Thickness Scaling Study of Phase Change Material

To address the scalability of phase change memory (PCM), we study a 1-D thickness scaling effect on threshold switching voltage (<i>V</i>_th), <i>V</i>_th drift, high resistance state (RESET) resistance (<i>R</i>_RESET) drift, and crystallization temperature (<i>T</i>_crys). We use a pseudo three-terminal device to accurately correlate the amorphous region thickness to the observed characteristics. The pseudo 3-terminal device is a fully functional PCM cell and enables 1-D thickness scaling study down to 6 nm without the need for ultrafine lithography. <i>V</i>_th scales down to 0.65-0.5 V (at 25°C-75°C) for 6-nm-thick Ge₂Sb₂Te₅ (GST), showing that stable read operation is possible in scaled PCM devices. The <i>V</i>_th drift measurement suggests that <i>V</i>_th drift can be attributed to threshold switching field (<i>E</i>_th) drift, whereas <i>V</i>_th0, i.e., <i>V</i>_th at zero thickness, stays almost constant. <i>R</i>_RESET drift shows no dependence on the amorphous GST thickness. <i>T</i>_crys is ~175°C for the device with 6-nm-thick GST, compared with ~145°C of thick GST. From the 1-D scaling study, no significant hurdles against scaling are found down to 6 nm. Further study of scaling effect on endurance and development of scalable selection device is needed to assess the ultimate scalability of PCM.

(\hbox{Ge}_{2}\hbox{Sb}_{2}\hbox{Te}_{5})

1D thickness scaling study on a-GST has been successfully demonstrated without the help of ultra-fine lithography. Vth linearly scales down to ∼0.65 V at 6 nm scale, showing that stable read operation is possible at elevated temperature (70 °C). Reset R drift shows no dependency on the a-GST thickness up to 6 nm regime. Thin a-GST shows enhanced thermal stability compared to thick a-GST.

Using a Pseudo 3-Terminal Device

We fabricated trench PbZrxTi1-xO3 (PZT) capacitors that can be used in 256Mbit 1T-1C FRAM devices. The capacitor has 0.25mum diameter and 0.4mum depth. Three layers, Ir(20nm)/PZT(60nm)/Ir(20nm), were deposited in SiO2 trench holes by ALD and MOCVD. Both columnar and granular grains were formed on the sidewalls of the trench capacitors, and their relative portion had strong size dependence. The trench capacitors with more columnar PZT grains showed good switching behavior under 2.1V external bias and 19 to 24 muC/cm2 remnant polarization

1D thickness scaling study of phase change material (Ge 2 Sb 2 Te 5 ) using a pseudo 3-terminal device

We investigated a novel technique of modifying the interface between a Pb(ZrxTi1-x)O3 (PZT) thin film and electrodes for high density 64 Mbit ferroelectric random access memory (FRAM) device. Using a SrRuO3 buffer layer, we successfully developed highly reliable 0.15 µm/14 F2 cell FRAM capacitors with 75-nm-thick polycrystalline PZT thin films. The SrRuO3 buffer layer greatly enhanced ferroelectric characteristics due to the decrease in interfacial defect density. In PZT capacitors with a total thickness of 180 nm for whole capacitor stack, a remnant polarization of approximately 42 µC/cm2 was measured with a 1.4 V operation. In addition, an opposite state remnant polarization loss of less than 15% was observed after baking at 150 °C for 100 h. In particular, we found that the SrRuO3 buffer layer also played a key role in inhibiting the diffusion of Pb and O from the PZT thin films.

Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application

For the first time, we successfully developed highly reliable 50nm-thick polycrystalline PZT capacitor using noble Ir/SrRuO/sub 3/ top electrode and MOCVD PZT technology. In the 50nm-thick PZT capacitor, 33/spl mu/C/cm/sup 2/ of remanent polarization and 0.7V of saturation voltage have been demonstrated. Moreover, after 100hrs of bake-time at 150/spl deg/C, opposite-state polarization margin was over 23/spl mu/C/cm/sup 2/, which is world-wide best result so far achieved. Using this capacitor technology, highly reliable low voltage operating embedded FRAM device was successfully developed.

Highly reliable 0.15 μm/14 F2 cell ferroelectric random access memory capacitor using SrRuO3 buffer layer

ABSTRACT In this paper, we first applied the Chemical Mechanical Polishing (CMP) and post-CMP cleaning processes to the planarization of ferroelectric film in order to obtain good planarity of electrode/ferroelectric film interface for ferroelectric random access memories (FRAM) applications. We investigated the structural and electrical characteristics of MOCVD PZT films grown on Ir bottom electrode before and after CMP process. The surface roughness of 100 nm PZT thin film was so distinctly reduced by CMP process that RMS and peak-to-valley values decreased from 4 nm and 50 nm to 0.2 nm and 5 nm, respectively. Moreover leakage current and retention characteristics of polished ferroelectric capacitors were improved by reducing PZT film roughness. Since high leakage current has been a main obstacle in operating thin PZT ferroelectrics, this indicates that PZT surface roughness produced by MOCVD process should be minimized for acquiring low voltage of FRAM application. No degradation in polarization hysteresis and fatigue characteristics of polished PZT capacitors was observed when favorable polishing process condition such as low down-pressure and slow table-speed was applied. In addition, post-CMP cleaning with an appropriate cleaning solution effectively removed slurries on PZT film without any further degradation. These results suggest that PZT CMP and post-CMP cleaning will be useful tool for acquiring highly-planarized thin MOCVD PZT film for next generation FRAM application.

Highly reliable 50nm-thick PZT capacitor and low voltage FRAM device using Ir/SrRuO/sub 3//MOCVD PZT capacitor technology

ABSTRACT Reliable ferroelectric 100 nm-thick PZT capacitors for 1.6 V operating FRAM device were successfully developed using MOCVD PZT with a PbTiO3 seed layer process. PbTiO3 seed layer process improved the opposite-state retention properties of polycrystalline PZT films by enhancing the (111) texture. We demonstrated that the same sensing-margin of FRAM device was obtained regardless of PbTiO3 seed layer insertion, while the retention properties were considerably improved.

STUDY ON ELECTRICAL PROPERTIES OF FLATTENED MOCVD PZT FILM BY CMP PROCESS

We newly developed a highly reliable 100 nm thick MOCVD PZT technology and a novel direct cell via technology applicable to fully logic compatible sub 10F/sup 2/ cell embedded FRAM. A 2Pr value of 40 uC/cm/sup 2/ at 1.6V was obtained on our one-mask etched new PTO seeded 100 nm thick MOCVD PZT capacitor. Capacitor degradation that could occur upon a direct application of metal on capacitor through direct via was completely prevented by combining a novel TiN-plug scheme and a diffusion barrier metal technology, which greatly improves the interface properties between top electrode and PZT. Finally, a highly reliable, 1.6V operational, sub 10F/sup 2/ cell FRAM has been successfully embedded into experimental 0.18 /spl mu/m logic with only two additional FRAM masks by successfully implementing the above two key technologies.

ENHANCED RETENTION PROPERTIES OF Pb(Zr,Ti)O3 THIN FILM BY APPLYING PbTiO3 SEED LAYER

Feasibility of high density probe-based memory with polycrystalline ferroelectric media has been demonstrated for next memory applications beyond sub-10 nm generation. Noble chemical-mechanical-polishing (CMP) method was employed to fabricate a very even surface on polycrystalline MOCVD Pb(Zr,Ti)O3 (PZT) media. On the CMP processed PZT media, domain dot array was able to be written and read even at grain boundary region by PFM technique. Moreover, 15 nm-sized domain dot was successfully demonstrated on 50 nm-thick PZT media. Also for the first time, we successfully demonstrated that the polycrystalline ultra thin 7 nm-thick PZT media has good ferroelectric properties

Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) highly reliable sub 10F2 embedded FRAM with advanced direct via technology and robust 100 nm thick MOCVD PZT technology

A novel method of metal-organic chemical vapor deposition (MOCVD) Pb(Zr,Ti)O3 (PZT) has been developed for use in high-density ferroelectric memory device. Well-aligned polycrystalline PZT films were grown onto Iridium bottom electrode by the MOCVD method with tmhd-family precursors in octane-based solvent under oxygen atmosphere at 550°C. Moreover, crystallinity of the PZT films on Ir bottom electrode was improved dramatically by inserting TiAlN barrier layer. It is also investigated the Iridium bottom electrode effect on the PZT in the ways of roughness, grain size, remnant polarization, fatigue and retention properties. Resultantly, highly reliable (111)-oriented PZT capacitors were obtained with 2Pr of 45 μC/cm2 and Vc of 0.8 V through MOCVD method and the interface engineering of the Iridium bottom electrode.