Ping-Ying Wang

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

A digital intensive PLL featuring a digital filter in parallel with an analog feed-forward path and a digital controlled oscillator (DCO) is presented. Digital loop filter replaces analog passive filter to reduce chip area and associated gate-leakage in advanced process. It also allows the PLL loop gain and DCO gain to be digitally calibrated to within 100 ppm within 50 mus. Such fine frequency resolution enables the PLL to accurately compensate for the loop parameter variation due to process, voltage and temperature (PVT). The analog feed-forward path is insensitive to quantization error of fractional-N divider and DCO nonlinearity. Direct modulating the DCO frequency and phase through the analog feed-forward path, and compensating the modulating signal digitally for the DCO gain variation are demonstrated. At 3.6 GHz all fractional spurs are under - 75 dBc. The phase noise at 400 kHz and 3 MHz are -115.6 dBc/Hz and -134.9 dBc/Hz, respectively. The chip is fabricated in a 0.13 mu m CMOS process, and occupies an active area of 0.85 mm2 and draws 40 mA from a 1.5 V supply including all auxiliary circuitry.

A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE

This paper presents a 3.2-to-4GHz fractional spur-free ADPLL. The ADPLL is fabricated in a 0.13 mum CMOS process and packaged in QFN76. Fractional spurs are filtered by accurate digital loop-gain calibration and digital phase-noise cancellation. The ADPLL is designed to minimize the switching noise while taking advantage of digital scaling.

15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO

Due to the high supply sensitivity of ring voltage-controlled oscillators (RVCOs) ([oscillation frequency change %] / [VDD change %] typically lies in the range from 1 to 2 [1]), an LDO has to provide over 40dB power-supply-rejection ratio (PSRR) to maintain VCO phase noise. However, the voltage dropout of an LDO consumes extra power and voltage headroom, which is unacceptable in low-voltage design. Moreover, the device noise from the LDO degrades the phase-noise performance. Recently published works [1-5] employ analog compensation techniques to lower supply sensitivity, and [2] incorporates a hybrid background calibration scheme for robustness. However, the additional current sources and active devices embedded in the oscillator [1-5] increase power and noise. In this work, a DCO with passive devices and all-digital calibration mitigates supply sensitivity under PVT variation, while maintaining phase noise and power consumption. The digital background-calibration logic regulates the oscillator supply to an optimally insensitive point by monitoring a digital loop filter (DLF) code, leveraging an advantage of an ADPLL [6].

10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter

Ring PLLs play an important role in mobile baseband applications. In cases where fine frequency resolution and low jitter are both needed, wideband fractional-N PLL architectures with quantization noise (Q-noise) cancellation are preferred. Phase interpolators (PI) are widely used in recent literature [1-3]. Although the Q-noise is reduced, decreasing supply voltages severely limit the linearity and noise of PI. In this paper, we present a switched-capacitor loop filter (SCLF) to solve this problem. The developed SCLF with correlated double sampling (CDS) keeps the output of the charge pump (CP) near-ground to improve its noise, linearity, and power-supply rejection ratio (PSRR). Furthermore, a calibrated 2b ADC is used to realize type-II operation.

A charge pump-based direct frequency modulator

The architecture of a charge pump-based direct frequency modulator (DFM) is proposed. Based on a hybrid time/digital fractional-N phase lock loop (PLL), this architecture has several advantages. First, the data rate is independent of the PLL loop bandwidth. Since the modulation signal does not need boosting, the digital pre-emphasis filter is removed and thus, information about the PLLs inverse transfer function is not needed. This also eliminates complicated calibration circuits for reducing the phase errors induced by the mismatch between the pre-emphasis filter and the PLL transfer function. The circuit complexity is further reduced because only an additional programmable charge pump is needed. Simulation results on a GMSK modulator demonstrate that the proposed architecture can achieve data rates 14 times greater than the loop bandwidth.

A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives

A PLL with a mixed mode loop filter is designed to suppress the need for a large size capacitor in an analog clock/data recovery circuit and eliminates the need for a high resolution digital controlled oscillator (DCO) in a digital clock recovery circuit. The value of the capacitor in the mixed mode loop filter is 1/4 to 1/256 of that of a conventional loop filter and frequency quantization errors are smaller than that of a 16 bit DCO. The design was verified in the read channel of a digital versatile disc system at 478 Mbps and in the partial-response maximum-likelihood (PRML) detectors for a Blu-ray disc system at 264 Mbps.

A 1V fractional-N PLL with nonlinearity-insensitive modulator

A 1V fractional-N PLL is proposed in 40nm technology. With modified VCO, it can be operated under 1V supply with wide tuning range and low supply sensitivity. Besides, conventional 3rd MASH SDM is sensitive to nonlinearity caused by analog path, generating in-band fractional spur that cannot be filtered by PLL loop. In order to lower the sensitivity to nonlinearity, a new type of modulator is proposed. Theorem derivation and simulation results show that this modulator is insensitive to 2nd-5th order nonlinearity. The measured in-band worst-case fractional and reference spur are -64.5dBc and -81dBc, respectively. The RMS jitter is 3.91ps under 5.85mW power consumption.

Chaos in delay locked loop

We prove existence of chaos in delay locked loops (DLL). It is the first time that the chaotic phenomenon in DLLs is reported. The DLL is designed to verify predictions of theory analysis. The prediction of the theory is confirmed by circuit simulation. The chip size is only 0.015mm 2, thus provides a low cost analog solution to randomize clock phases and simple circuits to study chaos

A CMOS multi-format read/write SoC for 7/spl times/Blu-ray/16/spl times/DVD/56/spl times/CD

An SoC for high-speed read and write functions is designed for multi-formats of 7/spl times/BD/16/spl times/DVD/56/spl times/CD at channel bit rates of 462/418/242Mbit/s. The data is detected by a PRML detector. The ECC CODEC for all formats is integrated as a single RS-CODEC. The SoC is implemented as a 30mm/sup 2/ die in a 0.18 /spl mu/m 1P6M CMOS process and consumes 1.0/0.9/0.7W in 7/spl times/BD/16/spl times/DVD/56/spl times/CD playback modes.