Jing-Lin Kuo

60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process

AThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital control interface (DCI). The 2 × 2 TX/RX phased arrays have been packaged with four antennas in low-temperature co-fired ceramic modules through flip-chip bonding and underfill process, and phased-array beam steering have been demonstrated. The entire beam-steering functions are digitally controllable, and individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in TX and 180 mW in RX and occupies an area of 3.74 mm2 in the TX integrated circuit (IC) and 4.18 mm2 in the RX IC. The beam-steering measurement results show acceptable agreement of the synthesized and measured array pattern.

A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P_sat of 13.8 dBm, P₁ _dB of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V_DD biased at 1.8 V. When V_DD is biased at 3 V, it exhibits P_sat of 18 dBm, P₁ _dB of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm². To the authors knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.

A 24 GHz low power VCO with transformer feedback

A K-band low power VCO fabricated by 0.13 µm CMOS technology is developed. By employing a NMOS cross-coupled pair with a transformer feedback, low phase noise under low dc power condition can be achieved at higher frequency. The VCO exhibits a 2.2 GHz frequency tuning range. The output power and the phase noise at 1 MHz offset are −10 dBm and −113 dBc/Hz, respectively. The dc power consumption is 0.6 V/3 mW. To authors knowledge, this performance achieves the best FOM in CMOS K-band VCOs.

A 24-GHz low power and high isolation active quasi-circulator

A 24-GHz novel active quasi-circulator is developed in TSMC 0.18-µm CMOS. We proposed a new architecture by using the canceling mechanism to achieve high isolations and reduce the circuit area. The measured insertion losses |S<inf>32</inf>| and |S<inf>21</inf>| are 9 and 8.5 dB, respectively. The isolation |S<inf>31</inf>| is greater than 30 dB. The dc power consumption is only 9.12 mW with a chip size of 0.35 mm².

A 60 GHz Broadband Low-Noise Amplifier With Variable-Gain Control in 65 nm CMOS

A 60 GHz low-noise amplifier (LNA) implemented in a 65 nm CMOS process is presented. Due to the use of a gain-boosted input stage and binary controlled attenuators, the LNA exhibits a broadband response and four programmable gain levels from 18.9 to 7.9 dB while maintaining impedance matching at the 60 GHz frequency band. The fabricated circuit consumes a dc current of 25 mA from a 1.8 V supply.

A 14∼23 GHz CMOS MMIC distributed doubler with a 22-dB fundamental rejection

A broadband MMIC frequency distributed doubler fabricated by 0.18-μm CMOS technology has been designed to operate from 14 to 23 GHz. In order to reject the fundamental signals, the traditional low-pass drain line was replaced by a high-pass structure. The topology can improve the fundamental rejection without additional balanced structure, thus the chip size can be minimized. This measured conversion loss is less than 14 dB and the fundamental rejection is better than 22 dB for the output frequency between 14 and 23 GHz. The chip size is only 0.54 × 0.38 mm2.

A 24 GHz CMOS power amplifier using reversed body bias technique to improve linearity and power added efficiency

The linearity and power added efficiency (PAE) of the power amplifier (PA) are improved by reversed body bias (RBB) using 0.18-µm CMOS technology and the bias dependence of the circuit performances is investigated. Negative bias to the bulk and forward bias to the deep n-well of the MOSFET devices are used to reduce the effects of the parasitic diodes and change the threshold voltage (Vth), leading to enhanced linearity and power added efficiency for the PA. The 24-GHz PA for demonstration is a two-stage design using cascode RF NMOS configuration with reverse body bias techniques have resulted in a maximum measured output power of 19 dBm, an OP1dB of 15.7 dBm, a PAE of 24.7%, and a linear gain of 19 dB when VDD and VDNW both biased at 3.6 V, and VBody biased at −3.6V. The chip size with all testing pads is only 0.56 × 0.67 mm2. To the authors knowledge, this is the first demonstration of the reversed body-bias applied to CMOS PAs and achieved significant improvement of PAE and OP1dB.

A W-band power amplifier in 65-nm CMOS with 27GHz bandwidth and 14.8dBm saturated output power

A W-band power amplifier in 65-nm CMOS technology is presented in this paper. This PA is a 3-stage common source design using thin film microstrip lines to realize the matching network. Choosing high-pass topology for the inter-stage matching network and low-pass matching for the input and output to compensate device frequency response, we achieve a wide band and high output power PA. From the measurement results, under 1.2 V supply voltage, the small signal gain of this PA is 12 dB with 27 GHz 3-dB bandwidth (79-106 GHz). The saturated output power is 14.8 dBm, and P1dB is 12.5 dBm. This W-band PA demonstrated widest bandwidth among the reported CMOS PA in this frequency regime, with state-of-the-art output power performance, and a miniature size.

Novel MMIC Power Amplifier Linearization Utilizing Input Reflected Nonlinearity

This paper introduces a novel method to generate an auxiliary third-order intermodulation (IM3) signal, which can be used in the linearization of power amplifiers (PAs) by canceling the output IM3 power. This auxiliary signal is simply achieved by exploiting the input reflected power of the main device, rather than obtained by conventional methods as driving a highly nonlinear device or subtracting the fundamental power from the output signal. It is demonstrated that substantial IM3 power can be reflected to the source with little reflected fundamental power under some input matching conditions of the device, and this feature can be utilized in the design of monolithic microwave integrated circuits (MMICs) targeting excellent linearity. A 25-GHz pHEMT power amplifier is designed and fabricated to exemplify the proposed technique. With the linearization, the OIP3 of the proposed PA increases by 14 dB from 25 to 39 dBm, and the output power enhances significantly, from 5 to 14 dBm with -40-dBc IM3 distortion and from 9 to 14 dBm with -40-dBc adjacent channel power ratio.

A 60 GHz Sub-Harmonic Resistive FET Mixer Using 0.13

A 56 to 66 GHz sub-harmonic resistive mixer using 0.13 μm CMOS technology is presented in this letter. This mixer exhibits a flat conversion loss of about -12 and -13 dB and good isolations between ports from 56 to 66 GHz for both down and up-conversion with a lowest LO power of 0 and -1 dBm. The 2LO-RF isolation is more than 27 dB even if IF input power exceeds 4 dBm, which results from the mechanism of connecting drain and body of the device. Besides, this mixer has a relatively high input P1dB and a 3 GHz IF bandwidth in each band defined in IEEE 802.15.3c standard.