Lan Nan

Design of 60- and 77-GHz Narrow-Bandpass Filters in CMOS Technology

This paper investigates the design and implementation of millimeter-wave narrow-bandpass filters in a standard 0.18- m CMOS technology. Filters with a measured 10% 3-dB bandwidth at 60 and 77 GHz are realized in a thin-film microstrip structure by using the lowest metallization layer as a ground plane. The impact of dissipation losses of the filters is also examined. It is found that the metallization losses in the coupled-line filter as well as the ground plane are the main reasons for the insertion loss.

Experimental Characterization of the Effect of Metal Dummy Fills on Spiral Inductors

In modern CMOS technologies, metal dummy fills are required to maintain metal density uniformity and to planarize the layers. As frequency increases, the effect of the metal dummy fills on the CMOS integrated circuits or components should be taken into account. This work presents experimental results of the effect of metal dummy fills on the microwave behavior of spiral inductors fabricated in a standard 0.18-mum CMOS technology. The influences on the equivalent model parameters and the Q-factor are characterized based on measured S-parameters of inductors with and without metal dummy fills.

A Wideband Scalable and SPICE-Compatible Model for On-Chip Interconnects Up to 110 GHz

A fully scalable and SPICE compatible wideband model of on-chip interconnects valid up to 110 GHz is presented in this paper. The series branches of the proposed multisegment model consist of an RL ladder network to capture the skin and proximity effects, as well as the substrate skin effect. Their values are obtained from a technique based on a modified effective loop inductance approach and complex image method. A CG network is used in the shunt branches of the model, which accounts for capacitive coupling through the oxide and substrate loss due to the electrical field, as well as the impact of dummy metal fills. The values of these elements are determined by analytical and semiempirical formulas. The model is validated by a full-wave electromagnetic field solver, as well as measurements. The simulated S-parameters of the model agree well with the measured S-parameters of on-chip interconnects with different widths and lengths over a wide frequency range from dc up to 110 GHz.

RF Noise of 65-nm MOSFETs in the Weak-to-Moderate-Inversion Region

In this letter, the RF noise performance of 65-nm MOSFETs with 60-, 90-, 130-, and 240-nm drawn gate lengths has been extensively investigated in the weak-to-moderate-inversion region for low-power and low-voltage (LPLV) applications. Noise measurements show that although the noise performance is directly related to gate length (Lg), it does not monotonically scale with the inverse of gate length. When biased in the weak-inversion region, a transistor with slightly relaxed gate length, instead of minimum gate length, will benefit from a smaller gate resistance and a smaller equivalent noise resistance Rn. The transistor transconductance (gm), output conductance (gd), unity current gain frequency (fT) , maximum frequency of oscillation (f max), and noise parameters are extracted as a function of the drain current density and compared among devices with different gate lengths.

60 GHz bandpass filters with small and large bandwidths using thin film coupled microstrip in 0.18-μm CMOS

In recent publications of millimeter wave filters in standard CMOS, only single designs have been shown, all with bandwidths exceeding 25%. Here we present the systematic design and implementation of 60 GHz bandpass filters with a broad range of bandwidths in a 0.18-mum CMOS technology. Experimental results show that filters with bandwidths larger than 50% achieve an insertion loss less than 3 dB. The insertion loss increases to 9 dB as the bandwidth decreases to 10%. Furthermore, the relationship between insertion loss and bandwidth is established through measurement and compared to theoretical predictions. The results facilitate important design trade-offs for bandpass filter in transceiver front-end applications.

Impact of Metal Dummy Fills on the Performance of CMOS Inductors

To meet the metal density and uniformity requirement, metal dummy fills are inserted on all metallization layers in modern CMOS technologies. These metal dummy fills can have a detrimental effect on the performance of IC components. In this paper, the impact of metal dummy fills on the equivalent circuit and the performance of on-chip spiral inductors is presented based on experimental data. A simple closed-form formula is further provided to account for the effect of metal dummy fills to update the model for inductors in the conventional environment without metal dummy fills.

Analysis of the drain thermal noise for deep submicron MOSFETs

Seven models for the drain thermal noise of deep submicron MOSFETs are compared in this paper. The models have been applied to MOSFETs with channel lengths ranging from 65 nm to 250 nm operating in the linear and saturation regions. It is found that under the same drain voltage and gate voltage, the drain thermal noise increases as the channel length reduces. All models predict different values for the drain thermal noise, although the trends are the same. The impact of the channel length modulation (CLM) effect and the hot-carrier effect on the drain thermal noise are quantitatively studied. It is demonstrated that these effects increase the drain thermal noise in deep submicron MOSFETs and most significantly for shorter gate MOSFETs.

RF Noise Modeling of CMOS 90nm Device Using Enhanced BSIM4 with Additional Noise Source

A practical methodology for accurately modeling RF noise performance of deep submicron CMOS technologies using BSIM4 model is presented in this paper. The noise characterization parameters are extracted from measurements from 1.0 GHz to 18.0 GHz performed on 90 nm RF CMOS device. Based on the foundry provided model, RF and low frequency noise are fitted with slightly tuned BSIM4 parameters and extrinsic parasitics. Then accurate noise modeling performance is achieved by just one additional frequency dependent noise source using the van der Ziel configuration to fit accurately the four noise parameters over wide range of frequencies and bias conditions.

Improved Microwave Modeling of CMOS Spiral Inductors with Metal Dummy Fills

In advanced CMOS technologies, the insertion of metal dummy fills is unavoidable due to stringent metal density process requirements. Therefore existing compact models for on-chip components need to be updated to accurately account for the effect of these metal dummy fills in CMOS RFIC designs. This paper proposes a simple but accurate method to predict the microwave behavior of on-chip spiral inductors with metal dummy fills. Experimental results show that the increase in the dioxide capacitance Cox is the dominant factor leading to the decrease in Qmax and fmax. Two methods are adopted to calculate the change in the dioxide capacitance of on-chip inductors due to the metal dummy fills. Good agreement is achieved between the predicted and measured performance of inductors with metal dummy fills by updating Cox in the conventional models.

Unloaded Q-Factors of thin film microstrip resonators in 0.18-µm CMOS for millimeter wave applications

Thin film microstrip (TFMS) lines have important applications in the design of CMOS microwave and millimeter wave circuits including on-chip filters and matching networks. In these circuits, the achievable passband insertion loss or the Q-factor of the matching networks are determined by the unloaded Q-factors of the TFMS lines. Since CMOS processes provide various possibilities for implementing TFMS lines due to the availability of multi-level metallizations, an optimum configuration needs to be determined. In this work, the two most viable configurations for the TFMS lines in a 0.18-mum CMOS process are compared by rigorous simulation and measurement of the unloaded Q-factors of the lambda/4 TFMS line resonators at 60 GHz over a broad range of characteristic impedances.