Subhash C. Rustagi

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.

Millimeter-Wave Bandpass Filters by Standard 0.18-

Millimeter-wave (mm-wave) bandpass filters are presented using the standard 0.18-mum CMOS process. Without any postprocessing steps, thin film microstrip (TFMS) structure is properly constructed on the low-resistivity silicon substrate, aiming at reducing the substrate loss and crosstalk to a large extent. Using the broadside-coupled scheme, a tight coupling is achieved so as to make up a class of low-loss and broadband TFMS bandpass filters in the mm-wave range. To achieve a small size, one-stage and two-stage filters with sinuous-shaped resonators are designed and fabricated. A good agreement between the predicted and measured results has been observed up to 110 GHz

\mu\hbox{m}

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (Lgges0.35 mum), exhibit excellent device performance with high ION/IOFF ratio (~106), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate

CMOS Technology

This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach. With matching of the drive currents of n- and p-MOSFETs using different gate lengths to achieve symmetric pull-up and pull-down, sharp ON- OFF transitions with high voltage gains (e.g., DeltaV OUT/DeltaV IN up to ~ 40 for V DD = 1.2 V) are obtained. The inverter maintains its good transfer characteristics and noise margins for wide range of V DD tested down to 0.4 V. Individual transistors show excellent subthreshold characteristics and drive currents. The results are discussed in light of the circuit performances reported for other advanced nonclassical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS-circuit functionality is thus demonstrated.

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

High-performance metal-insulator-metal capacitors using atomic layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are fabricated and characterized for RF and mixed-signal applications. The laminate capacitor can offer high capacitance density (12.8 fF//spl mu/m/sup 2/) up to 20 GHz, low leakage current of 4.9/spl times/10/sup -8/ A/cm/sup 2/ at 2 V and 125/spl deg/C, and small linear voltage coefficient of capacitance of 211 ppm/V at 1 MHz, which can easily satisfy RF capacitor requirements for year 2007 according to the International Technology Roadmap for Semiconductors. In addition, effects of constant voltage stress and temperature on leakage current and voltage linearity are comprehensively investigated, and dependences of quadratic voltage coefficient of capacitance (/spl alpha/) on frequency and thickness are also demonstrated. Meanwhile, the underlying mechanisms are also discussed.

CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.

RF, DC, and reliability characteristics of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors for Si RF IC applications

For the first time, we perform a systematic investigation of the fast components of dynamic negative biased temperature instability (DNBTI) in p-MOSFET with an ultrathin SiON gate dielectric. Experimental results unambiguously show a fast DNBTI component measured by a recently developed fast measurement method, and this component is due to trapping and detrapping of hole traps N/sub ot/ in SiON. The cumulative degradation increases with increasing stress frequency. Model simulations are in excellent agreement with all experimental data.

High-performance MIM capacitor using ALD high-k HfO 2 -Al 2 O 3 laminate dielectrics

This paper investigates the design and implementation of millimeter-wave narrow-bandpass filters in a standard 0.18- m CMOS technology. Filters with a measured 10% 3-dB bandwidth at 60 and 77 GHz are realized in a thin-film microstrip structure by using the lowest metallization layer as a ground plane. The impact of dissipation losses of the filters is also examined. It is found that the metallization losses in the coupled-line filter as well as the ground plane are the main reasons for the insertion loss.

Fast DNBTI components in p-MOSFET with SiON dielectric

We present a rigorously derived analytical Poisson solution for undoped semiconductors and apply the general solution to generic MOSFETs with two gates, unifying different types such as silicon-on-insulator (SOI) and symmetric and asymmetric double gate (s-DG and a-DG) structures. The Newton-Raphson method is used to solve surface-potential equations resulting from the application of boundary conditions to the general Poisson solution, with an initial guess that is very close to the exact solution. The universal initial guess can be used as an approximate explicit solution for fast evaluation, while the iterative solution can be used for benchmark tests. The results demonstrate the unification of surface-potential solutions having an accuracy of 10-15 V for SOI, a-DG, and s-DG MOSFETs, which are achieved within two to six iterations. Furthermore, the explicit solution yields less than 3.5% error for back-to-front-gate oxide thickness ratios larger than 25