Jinho Han

Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator

This brief presents a theoretical analysis of the stochastic reference clock generator (SRCG), which creates a clock like periodic signal from a random nonreturn-to-zero data sequence. The output of the SRCG can be utilized as a reference clock for frequency acquisition in dual-loop clock-and-data recovery circuits. A frequency-locked loop (FLL) subsequent to the SRCG guides the voltage-controlled oscillator frequency into the pull-in range of the phase-locked loop while suppressing the high-frequency phase noise of the SRCG. The phase noise and frequency offset of the SRCG-FLL pair are analyzed. The validity of the theoretical analysis is supported by results taken from a test chip.

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mVppd to 1.06 Vppd. RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10 -12 is 42 mVppd. The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10 -15 on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

One chip-low power digital-TCXO with sub-ppm accuracy

The digital TCXO (DTCXO) has been studied extensively because of its high frequency accuracy and rapid start-up time. The value of compensation capacitance used in the DTCXO is stored in ROM or calculated by computing circuit. In this work, ROM and computing circuit are integrated together to obtain the merit of both schemes; accurate value and high resolution of compensation capacitance, respectively. The DTCXO contains a temperature sensor, A/D converter, controller, EEPROM, capacitor bank, and oscillator. The oscillation frequency can be pulled from /spl plusmn/25 ppm to the required frequency with sub-ppm accuracy. The maximum power consumption of the total chip is 6.6 mW at 3.3 V. The chip, die size of 9mm/sup 2/, is fabricated by a 0.5 /spl mu/m CMOS technology.

0.6–2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique

A 0.6-2.7-Gb/s phase-rotator-based four-channel digital clock and data recovery (CDR) IC featuring a low-power dispersion-tolerant referenceless frequency acquisition technique is presented. A quasi-periodic reference clock signal extracted directly from a dispersed input signal is distributed to digitally controlled phase rotators in the CDR ICs for phase acquisition. A multiphase frequency acquisition scheme is employed for the reduction of the clock jitter. The measurement results show that the proposed design offers a lower frequency offset and clock noise floor under channel dispersion, as compared with conventional designs. The proposed four-channel digital CDR IC is fabricated in a 90-nm CMOS process. The figure of merit for a single channel is 8 mW/Gb/s such as a feedforward equalizer, a decision-feedback equalizer, and a referenceless CDR.

A

A four-parallel 10-Gb/s referenceless-and-masterless phase rotator-based transceiver is presented. Entire lanes operate independently just like the conventional voltage-controlled-oscillator-based parallel referenceless designs while saving power and area. The measured recovered-clock jitter in each lane is 1.24 psrms and the transceiver surpasses the OC-192 jitter-tolerance specification. The power efficiency of the proposed parallel transceiver fabricated in a 90-nm CMOS process is 6.325 mW/(Gb/s).

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With fluctuating voltage, widening operating temperature, and increasing clock frequency, cache systems are becoming increasingly susceptible to transient errors. Error correction code (ECC) is an attractive approach for transient error detection and correction. However, redundant memory for ECC has a significant impact on cost and increases the transient error rates. This brief presents a fault-tolerant cache system of automotive vision processors. The cache system has the small redundant memory and decreases the transient error rates with the proposed mechanism, which increases the error recovery rate and is considered with data cache characteristics. Also, the cache system is analyzed complying with ISO26262. As a result, thanks to 80% reduction of error traps caused by the cache system at the automotive vision processors variable fault-tolerant policy, compared to the cache system of the state-of-art vision processors for automotive.

-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS

With fluctuating voltage, widening operating temperature, and increasing clock frequency, cache systems are becoming increasingly susceptible to transient (soft) errors. Error correction code(ECC) is an attractive approach for transient error detection and correction[1]. However, redundant memory for error correction code has a significant impact on cost and increases the transient error rates. This paper presents a fault tolerant cache system of vision processors for automotive. The cache system has the small redundant memory and decreases the transient error rates. We proposed the mechanism which increases the error recovery rate and is considered with data cache characteristics.

A fault tolerant cache system of automotive vision processor complying with ISO26262

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of 80 μW/MHz. The operating frequency of the core reaches 850MHz at 1.2V.