Jinhyun Shin

A 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size using 90 nm flash technology

A manufacturable 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size, which is the smallest cell size ever reported in semiconductor memory, is successfully developed with 90 nm NAND flash technology for high density file storage application. The three main key technology features of 90 nm NAND flash technology are advanced KrF lithography with off-axis illumination system equipped with a dipole aperture, reduced stack height of cell, and optimized gate reoxidation affecting tunnel oxide profile.

A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory

A highly manufacturable multi-level NAND flash memory with a 27nm design rule has been successfully developed for the first time. Its unit cell size is 0.00375um2 (with overhead). Self Aligned Reverse Patterning is used to improve initial Vth distribution induced from DPT (Double Patterning Technology) process. By using advanced channel doping technique, the channel junction leakage is minimized and the Vpass window is improved. The optimized doping structure and cell operation scheme are evaluated. And finally 2 and 3bit per cell operation are successfully demonstrated with flash cells of 32Gb density with reasonable reliability.