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Dive into the research topics where Joanna Wasyluk is active.

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Featured researches published by Joanna Wasyluk.


Silicon-Germanium Technology and Device Meeting (ISTDM), 2014 7th International | 2014

Optimization of ISBD embedded SiGe layers to prevent delamination process for MOSFET applications

Joanna Wasyluk; Yang Ge; Kai Wurster; Markus Lenski; Carsten Reichel

Embedded strained SiGe (eSiGe) layers applied for source/drain applications enhance hole mobility of the transistor by inducing uniaxial compressive strain into Si-channel [1, 2], One of the common SiGe techniques used for source/drain (S/D) formation is in situ boron doped (ISBD) SiGe epitaxy. It is well known that ISBD eSiGe S/D device exhibits higher drive current than a boron-implanted eSiGe S/D device due to the fact that almost all B atoms locate into substitutional sites of SiGe lattice structure.


Archive | 2013

INTEGRATED CIRCUITS INCLUDING EPITAXIALLY GROWN STRAIN-INDUCING FILLS DOPED WITH BORON FOR IMPROVED ROBUSTNESS FROM DELIMINATION AND METHODS FOR FABRICATING THE SAME

Joanna Wasyluk; Carsten Reichel; Joachim Patzer; Kai Wurster


Archive | 2014

METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY PERFORMING A DRY CHEMICAL REMOVAL PROCESS

Frank Jakubowski; Joerg Radecker; Joanna Wasyluk


Archive | 2013

METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ROBUST GATE ELECTRODE STRUCTURE PROTECTION

Joanna Wasyluk; Dominic Thurmer; Ardechir Pakfar; Markus Lenski


Archive | 2012

METHODS FOR PFET FABRICATION USING APM SOLUTIONS

Joanna Wasyluk; Stephan Kronholz; Berthold Reimer; Sven Metzger; Gregory Nowling; John Foster; Paul R. Besser


Archive | 2014

Poly Removal for replacement gate with an APM mixture

Joanna Wasyluk; Paul R. Besser; Stephen Kronholz; Gregory Nowling; James Schaeffer


Archive | 2012

HORIZONTAL EPITAXY FURNACE FOR CHANNEL SIGE FORMATION

Joanna Wasyluk; Yew Tuck Chow; Stephan Kronholz; Lindarti Purwaningsih; Ines Becker


Silicon-Germanium Technology and Device Meeting (ISTDM), 2014 7th International | 2014

SiGe channel deposition by batch epitaxy

Carsten Reichel; Joerg Schoenekess; Andreas Dietel; Joanna Wasyluk; Yew Tuck Chow; Thorsten Kammler


Archive | 2014

INTEGRATED CIRCUITS WITH A BOWED SUBSTRATE, AND METHODS FOR PRODUCING THE SAME

Ralf Richter; Gerd Zschätzsch; Joanna Wasyluk


Archive | 2013

Method for manufacturing e.g. p-channel FET, for CPU, involves forming gate electrode structure above crystalline threshold voltage-adjusting layers, and forming drain and source regions of transistor in active region of transistor

Stephan Kronholz; Joanna Wasyluk; Yew Tuck Chow

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