Markus Lenski

Robust PEALD SiN spacer for gate first high-k metal gate integration

As we packed more and more transistors into one chip and as the size of transistor continues to shrink, the need for conformal sidewall protection layer becomes critical. In this work improved device properties is demonstrated using PEALD SiN spacer compared to the conventional PECVD SiN spacer.

Impact of precursors choice on characteristics of PEALD SiN for spacer applications

As transistor size continues to shrink, the need for conformal spacer which is insensitive to loading condition arises. Previously we have reported improved device characteristics for transistors with PEALD SiN spacer compared to those with CVD SiN spacer. In this work characteristics of PEALD SiN spacer deposited with liquid or gas precursors is studied. Good device properties are obtained with both precursor types, with slightly better iso-loading characteristics for devices with SiN deposited using liquid precursor.

Optimization of ISBD embedded SiGe layers to prevent delamination process for MOSFET applications

Embedded strained SiGe (eSiGe) layers applied for source/drain applications enhance hole mobility of the transistor by inducing uniaxial compressive strain into Si-channel [1, 2], One of the common SiGe techniques used for source/drain (S/D) formation is in situ boron doped (ISBD) SiGe epitaxy. It is well known that ISBD eSiGe S/D device exhibits higher drive current than a boron-implanted eSiGe S/D device due to the fact that almost all B atoms locate into substitutional sites of SiGe lattice structure.