Carsten Reichel

Facet engineering for SiGe/Si stressors in advanced CMOS technology

A two-layer SiGe stressor was introduced for our CMOS technology containing a layer with high Ge content to induce more stress to the channel and on top a layer with lower Ge content for better silicidation [1]. The SiGe is grown undoped prior to the transistor implants to give optimal control of the dopant profile while keeping SiGe close to the gate [2]. However, the silicidation became more critical for more advanced technology node. A very high number of defects were found after silicidation of the SiGe top layer causing severe contact punch through. It was not feasible to achieve the required quality of the silicide using a SiGe cap.

Optimization of ISBD embedded SiGe layers to prevent delamination process for MOSFET applications

Embedded strained SiGe (eSiGe) layers applied for source/drain applications enhance hole mobility of the transistor by inducing uniaxial compressive strain into Si-channel [1, 2], One of the common SiGe techniques used for source/drain (S/D) formation is in situ boron doped (ISBD) SiGe epitaxy. It is well known that ISBD eSiGe S/D device exhibits higher drive current than a boron-implanted eSiGe S/D device due to the fact that almost all B atoms locate into substitutional sites of SiGe lattice structure.