Joanne Huang

Extending drift-diffusion paradigm into the era of FinFETs and nanowires

This paper presents a feasibility study that the drift-diffusion model can capture the ballistic transport of FinFETs and nanowires with a simple model extension. For FinFETs, Monte Carlo simulation is performed and the ballistic mobility is calibrated to linear & saturation currents. It is validated that the calibrated model works over a wide range of channel length and channel stress. The ballistic mobility model is then applied to a nanowire with 5nm design rules. Finally, the technology scaling trend of the ballistic ratio is explored.

Modeling and optimization of group IV and III–V FinFETs and nano-wires

We described simulation methodologies involving a variety of modeling techniques applied to design and optimization of several key aspects of the 7nm and 5nm transistors and standard library cells. Analysis of channel material engineering for the 7nm FinFETs points to different trade-offs for the HP, SP, and LP leakage specs. Mechanical stability of the fins with high aspect ratio is evaluated as a major factor determining fin shape engineering and transitions from bulk FinFET to SOI FinFET and then to NW. Comparative analysis of the 10 track high 2-input NAND library cells based on different channel materials, different spacer materials, and different transistor architectures suggests that the largest benefits of 3.6x speed gain with 5x reduction in power consumption is achieved by switching from 7nm Si baseline FinFET process to 5nm vertical Si NWs. Within lateral transistors at 7nm design rules, transition from fins to lateral NWs and replacing nitride spacers with oxide spacers offer significant speed/power advantage. The channel material engineering brings the weakest advantage on the library cell level.

Experimental and theoretical analysis of the optical behavior of textured silicon wafers

Optical analysis is performed for mono-crystalline silicon wafers with and without the texture and with and without the POCl doping, the passivating anti-reflective nitride film on front surface, and the screen printed aluminum conductor on the back surface. Reflectance is measured in the wavelength range from 300 nm to 1200 nm. Modeling of the light reflectance, absorbance, and transmittance is done using ray-tracing technique for the regular and the random texture patterns. Good agreement of measured and modeled data is obtained for the sub — 1 micron wavelengths by using standard material optical properties. However, the infrared light above the 1 micron wavelength requires accounting for several mono-layers thick native oxide present on silicon surfaces and adjusting the optical properties of specific nitride and aluminum films used in the solar cell manufacturing. It is found that the random texture exhibits 15% to 20% better light capture than the regular texture. Theoretical analysis provides plausible explanation of this effect and suggests a way to further improve optical performance of the textured surfaces. The optical modeling methodology can be used to find the optimum combination of texture and passivating/contact films for different solar cell designs.

Transistor design for 5nm and beyond: Slowing down electrons to speed up transistors

Analysis of the key band structure properties for MOSFET channel material are investigated in a wide range for nanowires with design rules scaling from 5 nm down to 2 nm. Three-dimensional Non-Equilibrium Greens Functions (NEGF) method is employed to calculate the on-state currents for different channel band structures. Results of the analysis show that the optimal effective mass increases with transistor scaling from 0.1 at 5 nm design rules up to 0.4 at 2 nm design rules. There is a gentle performance degradation for effective masses that are heavier than optimal, and there is a steep performance penalty for the lighter electrons due to the direct source-to-drain tunneling through the source junction barrier. Different Si crystal orientations can be chosen to get close to theoretically possible optimal performance, or stress can be used to slow down the electrons. Silicon scales well down to at least 2 nm technology node, and properties of typical 2D materials like MoS2 are close to optimal. However, high-mobility materials like Ge or III-V are far outside of the optimal property range and do not scale well. One other key aspect of transistor scaling potential is its inherent random variability. Analysis of transistor performance sensitivity to geometry fluctuations shows that nanowires with 5 nm design rules are less sensitive than FinFETs to the channel length variation, but sharply more sensitive than FinFETs to fin width variation. Specific FinFET and nanowire sensitivity to geometry fluctuations can be used to determine the spec for future equipment that is necessary for high yield nanowire manufacturing.

FinFET/nanowire design for 5nm/3nm technology nodes: Channel cladding and introducing a “bottleneck” shape to remove performance bottleneck

Transition from planar MOSFETs to FinFETs enabled scaling beyond 28nm node. At 5nm/3nm design rules, a transition from FinFETs to nanowires has to be evaluated. We explore with rigorous NEGF (Non-Equilibrium Greens Functions) and sub-band Boltzmann transport models the impact of nanowire shape and SiGe/Si cladding layers on its performance and variability. Outside of the nanowire channel, a “bottleneck” shape of the source/drain extensions can either boost or ruin the performance, requiring NEGF-driven meticulous shape engineering.

Power-performance-area engineering of 5nm nanowire library cells

We benchmark planar MOSFETs, FinFETs, and nanowires in a wide range of design rules, spanning from 90nm down to 2nm. This benchmarking evaluates inverter switching speed for a load of 70 metal pitches long interconnect wire and a fan-out of one. Planar MOSFET logic slows down sharply at 14nm design rules, mainly due to short-channel effects reducing the driving strength at a fixed off-state leakage level. FinFETs take over at 14nm node and continue providing incremental gains down to 7nm design rules, but slowing down at 5nm due to the dominant parasitic middle-of-line capacitance. Vertical nanowires take over the lead at 5nm design rules and scale gracefully down to at least 5nm node. Based on these results, we perform detailed benchmarking of several design and process options for a 2-input NAND logic cell built on vertical nanowires with 5nm design rules. Benchmarking involves a holistic modeling methodology with 3D advanced carrier transport characterization of the nanowire behavior, 3D extraction of parasitic RC in the library cell, and simulation of power and delay of an 11-stage ring oscillator in HSPICE. Different cell designs and material engineering options offer cell area reduction of 33% with delay and power changing by over 2x.

Selective and homo emitter junction formation using precise dopant concentration control by ion implantation and microwave, laser or furnace annealing techniques

We investigated phosphorus and boon implanted emitter and selective emitter junction formation comparing; 1) 15keV to 30keV implant energies, 2) implant dopant dose concentration between 3E14/cm2 to 1E16/cm2 and 3) various anneal conditions from high temperature (>;1407°C) laser melt annealing to low temperature (<;500°C) microwave annealing and furnace anneals between 750°C to 1050°C for dopant activation and diffusion. By engineering and optimizing dopant concentration with anneals we could realize homo emitter and selective emitter junctions from 0.25um to 1.5um depth with sheet resistance from 9Ω/□ to 2200Ω/□ and peak surface dopant electrical activation levels from 4E18/cm3 up to 5E20/cm3. Highest dopant activation efficiency was achieved with liquid phase junction diffusion formation method using laser melt annealing and was limited by the dopant source concentration if <;E16/cm2. The POCl3 dopant source concentration of 1E16/cm2 was only 15% efficient with furnace solid phase diffusion activation while laser melt liquid phase diffusion activation was 45% compared to implant which was 35% active with solid phase diffusion and 100% active with liquid phase diffusion.

Mono-Crystalline Silicon Solar Cell Optimization and Modeling

With point contacts on the rear surface of a solar cell, several competing physical mechanisms determine its performance. On the one hand, different optical reflectivity and surface recombination rates for the silicon-aluminum interface and passivated silicon-nitride interface suggest that reducing rear contact area would boost cell efficiency. On the other hand, current crowding, contact resistance, and bulk recombination will contribute to cell performance degradation with shrinking rear contact area. Furthermore, the trade-off between these factors will be affected by any change in doping, silicon quality and cell size. Therefore, there is a large optimization space to find the best solar cell design.

Performance analysis of p-type silicon nanowire FETs with silicon-germanium cladding

The performance of p-type silicon nanowire FETs with three different silicon-germanium cladding options is bench-marked against the silicon reference device. Low-field mobilities and full device characteristics are obtained from the solution of the subband Boltzmann transport equation, including phonon and surface roughness scattering. The subband dispersion is calculated using 6kp band structure model, including the strain induced by the cladding layer. We show that silicon nanowires can be outperformed due to the superior hole mobility of strained silicon-germanium, but the off-state behavior degrades with increasing cladding thickness.

Modeling and Optimization of Solar Cells

A methodology is presented for modeling textured wafers, junction engineering for POCl3 and ion-implanted junctions, and electrical performance of the novel solar cell architectures with 3D current crowding. The important design and process trade-offs are demonstrated that enable to make cost-efficient choices to maximize the overall solar cell performance and cost per Watt. The 3D diffusion model is used for the junction formation on textured surfaces, and 3D carrier transport with recombination and traps is used for the electrical analysis.