Munkang Choi

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Effectiveness of Stressors in Aggressively Scaled FinFETs

The stress transfer efficiency (STE) and impact of process-induced stress on carrier mobility enhancement in aggressively scaled FinFETs are studied for different stressor technologies, substrate types, and gate-stack formation processes. TCAD simulations show that strained-source/drain STE is 1.5× larger for bulk FinFETs than for SOI FinFETs. Although a gate-last process substantially enhances longitudinal stress within the channel region, it provides very little improvement in electron mobility over that achieved with a gate-first process. Guidelines for FinFET stressor technology optimization are provided, and performance enhancement trends for future technology nodes are projected.

Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology

This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.

Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks

S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled FinFETs. Not merging the S/D epitaxy between adjacent fins and recess etch into the fin before S/D epitaxy is recommended for maximizing the gain. With high active P concentration Si:C becomes an effective stressor for NMOS. Contact and gate metal fills provide new knobs for engineering strain in FinFET devices for the 22nm node and remain effective with conservative scaling of contact / gate CD only.

Analysis of microbump induced stress effects in 3D stacked IC technologies

Besides the stress around Cu TSVs, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting FETs through the thinned silicon die and the stress on the thin die caused by 3D stacking. We find that the FET current shifts reach over 40% due to the impact of stress. Additionaly, a FEM parametric study was performed to determine key stress reduction contributors in 3D stacks.

Extending drift-diffusion paradigm into the era of FinFETs and nanowires

This paper presents a feasibility study that the drift-diffusion model can capture the ballistic transport of FinFETs and nanowires with a simple model extension. For FinFETs, Monte Carlo simulation is performed and the ballistic mobility is calibrated to linear & saturation currents. It is validated that the calibrated model works over a wide range of channel length and channel stress. The ballistic mobility model is then applied to a nanowire with 5nm design rules. Finally, the technology scaling trend of the ballistic ratio is explored.

Modeling and optimization of group IV and III–V FinFETs and nano-wires

We described simulation methodologies involving a variety of modeling techniques applied to design and optimization of several key aspects of the 7nm and 5nm transistors and standard library cells. Analysis of channel material engineering for the 7nm FinFETs points to different trade-offs for the HP, SP, and LP leakage specs. Mechanical stability of the fins with high aspect ratio is evaluated as a major factor determining fin shape engineering and transitions from bulk FinFET to SOI FinFET and then to NW. Comparative analysis of the 10 track high 2-input NAND library cells based on different channel materials, different spacer materials, and different transistor architectures suggests that the largest benefits of 3.6x speed gain with 5x reduction in power consumption is achieved by switching from 7nm Si baseline FinFET process to 5nm vertical Si NWs. Within lateral transistors at 7nm design rules, transition from fins to lateral NWs and replacing nitride spacers with oxide spacers offer significant speed/power advantage. The channel material engineering brings the weakest advantage on the library cell level.

Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime

We report for the first time the impact of 3D IC process induced local thermo-mechanical stress effects on CMOS devices for 7nm technology node (N7) operating in the ballistic regime. We show that the ballistic current is less affected by the uniaxial stress than the drift current. The ballistic current ratio decreases for longer gate, it is 80%, 45% of the total current for respectively 14nm and 40nm gate lengths devices resulting in larger TSV proximity effects for longer devices. 4 point bending measurements for Ge channel p-FinFETs, confirm the simulated stress sensitivities used to provide a physical estimation of the Keep Out Zone (KOZ). For high mobility channel devices, whereas N7 p-FinFETs exhibits similar TSV stress sensitivities, the KOZ for n-FinFETs is a function of the channel material choice for the co-integration. Unstrained Ge n-FinFETs are largely affected by the TSV proximity, 40% more than Si, SiGe and strained Ge n-FinFETs. Materials like Ge and InGaAs have a reduced sensitivity to the vertical stress component whereas the impact is significant in the case of Si and SiGe n-type devices, with more than 10% change in drive current for 400MPa compressive vertical stress.

14 nm FinFET Stress Engineering with Epitaxial SiGe Source/Drain

To summarize, this paper explores key challenges of FinFET stress engineering that is based on the epitaxial SiGe S/D. These challenges are FinFET-specific and can be addressed by carefully balancing several design and process trade-offs simultaneously. An appropriate 3D modeling methodology is demonstrated to handle the new FinFET-specific design and process challenges.

Noise coupling between TSVs and active devices: Planar nMOSFETs vs. nFinFETs

Through Silicon vias (TSVs) are a key breakthrough in 3D technology to shorten global interconnects and enable the heterogeneous integration. However, TSVs also introduce an important source of noise coupling arising from electrical coupling between TSVs and the active devices. This paper investigates the TSV noise coupling to active devices including both FinFETs and planar transistors based on two-port S-parameter measurements up to 40 GHz. The measurements clearly show that nFinFETs have better noise coupling immunity than planar nNMOSFETs. The dominant coupling mechanisms were also identified for both types of active devices. Moreover, calibrated TCAD models were developed. We show that via-last TSV architectures with thick liners (“donut TSVs”) and scaled TSV diameters reduce the noise coupling to active devices. Finally, both coupling and stress induced saturation current variations as a function of TSV to active devices distance were investigated. This allows us to propose a novel model for the TSV Keep Out Zone (KOZ) including electromagnetic coupling effects.