João C. Vital

Kickback noise reduction techniques for CMOS latched comparators

The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.

Systematic design for optimization of high-speed self-calibrated pipelined A/D converters

High-speed pipelined analog-digital converters have been previously considered using optimum 1-bit per stage architectures that typically can attain untrimmed resolution of up to 10 bits. Conversion resolutions higher than 10 bits can only be achieved if calibration techniques are employed. In this case, however, this paper demonstrates that multibit, rather than single-bit resolution per-stage architectures have to be considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks. Such optimization is achieved through a systematic design process that takes into account physical limitations for practical integrated circuit implementation, including thermal noise and capacitor matching accuracy. The impact of the selected pipelined configuration on the self-calibration requirements as well as on the practical feasibility of the active components is analyzed. An example is presented to consolidate the relevant conclusions.

Low kickback noise techniques for CMOS latched comparators

The latched comparator is utilized in virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. Such high voltage variations in the regeneration nodes are coupled to the input voltage - kickback noise. This paper reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations verify the effectiveness of our techniques.

Averaging technique in flash analog-to-digital converters

The averaging technique is used in flash analog-to-digital converters to reduce nonlinearities resulting from random offset voltages of the pre-amplifiers, which stand before the comparators. The main contribution of this paper is to provide further insight into this technique, through exact closed-form expressions obtained for the output voltage, gain, integral nonlinearity and differential nonlinearity in averaged pre-amplifiers. These theoretical results are compared with HSPICE simulations, and a very good agreement is found. Finally an automatic design procedure is described, which is based on the expressions derived, and a design example is given.

The MOS capacitor amplifier

It is well known that low noise amplification can be performed by using a capacitor whose capacitance can be controlled. In this paper, it is shown that changing the inversion level of a MOS transistor allows voltage amplification. The theoretical characterization of this amplifier in terms of gain and harmonic distortion is made, and comparisons with HSPICE results are performed. Finally, some practical considerations to improve the performance of the circuit are presented.

A SKILL/sup TM/-based library for retargetable embedded analog cores

This paper describes the automatic generation and reusability of physical layouts of analog and mixed-signal blocks based on high-functionality pCells that are fully independent of technologies. The high-functionality pCell library presently contains over 42 pCells and is fully compliant with 7 different sets of technology design rules from 5 different foundries. Practical examples employed in industrial projects are illustrated.

A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction

High-resolution pipeline analog-to-digital converters usually employ digital correction techniques to relax the requirements of the flash comparators, thus improving the performance of the converter. This paper exploits the same used common digital techniques to the class of non-linear ADCs, and in the special case of a true logarithmic pipeline converter. While the logarithmic operation is achieved by replacing the linear operations of subtraction and multiplication by simple scaling operations, the use of digital error correction allows to achieve high resolution and high dynamic range. An example is given to illustrate the proposed technique.

An analogue self-calibration technique for high-resolution video-rate pipelined A/D converters

An analogue self-calibration technique employing a high-linearity pulse-counting reference DAC for code-by-code correction is proposed for calibrating both the MDAC nonlinearities and the interstage-gain errors in high-resolution video-rate pipelined analogue-to-digital converters. When compared with alternative code-by-code calibration techniques, the proposed solution has the advantage of correcting also the residue-amplification gain of the calibrated stages while using similar additional resources. An example is presented which reveals the effectiveness of such solution.

Automatic multi-level macromodel generation for data conversion systems employing binary-weighted capacitor-arrays

Describes the generation of nonideal subcircuit behavioral models and macromodels for data conversion systems employing binary-weighted capacitor-arrays. The behavioral simulation is capable of performing a Monte Carlo analysis of the circuit under evaluation as well as determining the spectral characteristics of the converted signals and the resulting integral nonlinearity and differential nonlinearity. The behavioral simulation is event-driven-oriented to achieve improved time-efficiency in comparison which Spice-like mixed-mode simulators. It is demonstrated that the accuracy of the simulation results obtained with the proposed macromodels matches the accuracy of the results obtained through behavioral and mixed analog-digital simulation, and a significant improvement in the simulation time is achieved.<<ETX>>

A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications

This paper describes a pipeline 15-b 10 Ms/s analog-to-digital converter in a 0.35 /spl mu/m digital CMOS technology, suitable for ADSL applications. The architecture is based on a 5.5-bit front-end stage with a current-steering DAC and a continuous-time residue amplification followed by a 10-bit conventional pipeline backend ADC. The linearity is determined by the matching accuracy of the unit current sources, which can be controlled by the area and overdrive voltage of transistors. At Nyquist sampling (5 MHz) the signal-to-noise-and-distortion (SNDR) is 78.6 dB. The ADC has a differential input rang of 1.1 V and dissipates 320 mW from a 3.3 V power supply.