Jorge Guilherme

Analog circuits optimization based on evolutionary computation techniques

This paper presents a new design automation tool, based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.

Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques

The microelectronics market trends present an ever-increasing level of complexity with special emphasis on the production of complex mixed-signal systems-on-chip. Strict economic and design pressures have driven the development of new methods to automate the analog design process. However, and despite some significant research efforts, the essential act of design at the transistor level is still performed by the trial and error interaction between the designer and the simulator. This book presents a new design automation methodology based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.

Reconfigurable multi-mode sigma-delta modulator for 4G mobile terminals

A reconfigurable sigma-delta modulator, which is able to support the predictable standards for the fourth generation (4G) of mobile communication systems, is presented in this paper. This modulator was designed to cope with six different communications standards relying on a flexible architecture. Furthermore, the proposed architecture introduces the ability to process concurrently two different signals. The major design issues are outlined and operation modes are detailed. The feasibility of the presented solution is demonstrated using high-level system-level simulations as well as device-level simulations of the modulator implemented with switched capacitor circuits.

AIDA: Automated analog IC design flow from circuit level to layout

This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to a physical layout description. AIDA results from the integration of two in-house tools, namely, GENOM-POF and LAYGEN II. GENOM-POF performs fully automated circuit-level synthesis implemented with a multi-objective multi-constraint optimization approach, which addresses robust design requirements by considering Corners analysis together with an electrical simulator as the evaluation engine. LAYGEN II implements a DRC proved fully automated layout generation based on a sized circuit-level description and high level layout guidelines, described in a technology independent abstract layout template. The expert knowledge is used by LAYGEN II to guide the evolutionary optimization kernels during the automatic layout generation. Moreover, evolutionary computation techniques are extensively used, at both circuit-level and physical-level, as tool to solve design optimization problems. Finally, AIDA environment is demonstrated for the IC design of a classical circuit-level topology and state-of-the-art technology, and validated by industrial simulators and analysis tools, such as, HSPICE® and CALIBRE®.

New CMOS logarithmic A/D converters employing pipeline and algorithmic architectures

New techniques for realizing CMOS logarithmic analog-to-digital (A/D) converters employing pipeline and algorithmic architectures are described. This is achieved by replacing the operations of subtraction/addition and multiplications in their linear counterparts by simple scaling operations in the logarithmic domain. Logarithmic pipeline A/D converters are more appropriate for high-frequency applications whereas logarithmic algorithmic A/D converters are particularly suitable for compact, low-cost designs. Examples are given to illustrate the proposed techniques.

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC

A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.

GA-SVM feasibility model and optimization kernel applied to analog IC design automation

An efficient use of macromodeling techniques is pointed out as an effective approach to improve the convergence and speed of the optimization process. The methodology presented in this paper is based on a learning scheme using Support Vector Machines(SVMs) that together with and an evolutionary strategy is used to create efficient models to estimate and optimize the performance parameters of analog and mixed-signal ICs. The SVM is used to identify the feasible design space regions while at the same time the evolutionary techniques are looking for the global optimum. Finally, the proposed optimization based methodology is demonstrated for the design of a well known class of CMOSoperational amplifier topologies. The efficiency of the proposed approach is compared with standard and modified genetic algorithm kernels.

LAYGEN - Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions

This paper describes an innovative analog IC layout generation tool based on evolutionary computation techniques. The proposed approach starts by a high level layout description (template), which is independent from technology, although including expert knowledge as placement and routing constrains. Then, based on the set of constrain rules provided by the designer through the template, the layout is automatically generated using an evolutionary kernel. Additionally, a module generated is also included in order to allow the automatic generation of different instances for each device in the layout template, therefore, automatically enlarging the solution search space. The LAYGEN tool is here presented and demonstrated for the layout generation of typical circuit structures

A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction

High-resolution pipeline analog-to-digital converters usually employ digital correction techniques to relax the requirements of the flash comparators, thus improving the performance of the converter. This paper exploits the same used common digital techniques to the class of non-linear ADCs, and in the special case of a true logarithmic pipeline converter. While the logarithmic operation is achieved by replacing the linear operations of subtraction and multiplication by simple scaling operations, the use of digital error correction allows to achieve high resolution and high dynamic range. An example is given to illustrate the proposed technique.

An evolutionary optimization kernel with adaptive parameters applied to analog circuit design

This paper presents a new evolutionary optimization kernel applied to the automatic synthesis of high performance analog and mixed-signal ICs. This enhanced evolutionary approach is based on a modified genetic algorithm with self adaptive parameters tailored to efficiently control the optimization process. Particularly, the benefits introduced by self adaptive parameters consist of, first, reducing the problem complexity by using a grid with an adaptive resolution or step to describe the search space, then, improving the circumvention of local minima by including an adaptive mutation operator. The enhanced optimization kernel were tested for a broad range of well known test functions and compared to other approaches using MATLAB. Finally, the proposed optimization-based approach is demonstrated for the design of high-performance differential amplifiers using HSPICE as the evaluation engine.