Joel L. Seligson

Manufacturing considerations for implementation of scatterometry for process monitoring

The continuing demand for higher frequency microprocessors and larger memory arrays has led to decreasing device dimensions and smaller process control windows. Decreasing process control windows have created a need for higher precision metrology to maintain an acceptable precision to tolerance ratio with a reasonable sampling rate. In order to determine and reduce across chip, across wafer, and across lot linewidth variations, higher sampling is required which, in turn, demands faster move acquire measure (MAM) times to maintain throughput. Finally, the need to detect and quantify sidewall angle changes in addition to CD measurements is becoming critical. Spectroscopic Scatterometry is a metrology technique which offers the potential to meet these requirements. This work explores some of the fundamental technology concerns for implementing scatterometry in a manufacturing environment. These concerns include mark requirements and characterization necessary for library generation. Comparison of scatterometry data to in-line CD SEM, x-section SEM, and AFM results will be presented.

Diffraction order control in overlay metrology : a review of the roadmap options

Resolution enhancement in advanced optical lithography will reach a new plateau of complexity at the 32 nm design rule manufacturing node. In order to circumvent the fundamental optical resolution limitations, ultra low k1 printing processes are being adopted, which typically involve multiple exposure steps. Since alignment performance is not fundamentally limited by resolution, it is expected to yield a greater contribution to the effort to tighten lithographic error budgets. In the worst case, the positioning budget usually allocated to a single patterning step is divided between two. A concurrent emerging reality is that of high order overlay modeling and control. In tandem with multiple exposures, this trend creates great pressure to reduce scribeline target real estate per exposure. As the industry migrates away from metrology targets formed from large isolated features, the adoption of dense periodic array proxies brings improved process compatibility and information density as epitomized by the AIM target1. These periodic structures enable a whole range of new metrology sensor architectures, both imaging and scatterometry based, that rely on the principle of diffraction order control and which are no longer aberration limited. Advanced imaging techniques remain compatible with side-by-side targets while scatterometry methods require grating-over-grating targets. In this paper, a number of different imaging and scatterometry architectures are presented and compared in terms of random errors, systematic errors and scribespace requirements. It is asserted that an optimal solution must combine the TMU peak performance capabilities of scatterometry with the cost of ownership advantages of target size and multi-layer capabilities of imaging.

Target noise in overlay metrology

We have developed a method for calculating the statistical effects of spatial noise on the overlay measurement extracted from a given overlay target. The method has been applied to two kinds of overlay targets on three process layers, and the new metric, Target Noise, has been shown to correlate well to the random component of Overlay Mark Fidelity. A significant difference in terms of robustness has been observed between AIM targets and conventional Frame-in-Frame targets. The results fit well into the spatial noise hierarchy presented in this paper.

Overlay mark performance : a simulation study

The overlay budgets in leading-edge processes are expected to shrink below 20nm within the next 12-24 months. The demand for ever higher accuracies of overlay metrology for the 65nm node and below drive the development and design of new optical metrology solutions. In this work, we present new results as a continuation of the work we have previously reported on an overlay metrology simulation platform, capable of simulating the entire overlay measurement process. The simulation platform is used for modeling both the optical effects of the overlay metrology tool and the target process and design related effects on the overlay metrology performance. Using this simulation platform we have modeled target proximity effects limiting target size reduction, and process variation effects on overlay performance.

TIS-WIS interaction characterization on overlay measurement tool

Modern overlay metrology tools achieve the required metrology accuracy by controlling critical asymmetries in the imaging optics, and by compensating for the remaining asymmetries through TIS-calibration. We extend our study on the TIS-WIS interaction in stepper alignment optics to the overlay metrology tool, and propose a new method for characterizing residual TIS. This method is based on the examination of the through-focus behavior of the metrology tool on a wafer with a simple, TIS-sensitive structure.

Overlay metrology simulations: analytical and experimental validations

We have previously reported on an overlay metrology simulation platform, used for modeling both the effects of overlay metrology tool behavior and the impact of target design on the ultimate metrology performance. Since our last report, the simulation platform has been further enhanced, consisting now of eleven PCs and running commercial software both for lithography (PROLITH) and rigorous Maxwell calculations (EM-Suite). In this paper we report on the validation of the metrology simulations by comparing them to both analytical calculations and to experimental results. The analytical validation is based on the classical calculation of the diffraction of a polarized plane wave from a perfectly conducting half plane. For the experimental validation, we chose an etched silicon wafer manufactured by International SEMATECH (ISMT) and characterized at National Institute of Science and Technology (NIST). The advantages of this wafer are its well known topography and its suite of different metrology targets. A good fit to both analytical and experimental results is demonstrated, attesting to the capabilities of our enhanced simulation platform. The results for both the analytical and experimental validations are presented.

Overlay accuracy: a metal layer study

While overlay precision has received much focus in the past, overlay accuracy has become more significant with shrinking process budgets. One component of accuracy is the difference between pre-etch (DI) and post-etch (FI) overlay, which is a function of wafer processing parameters. We investigated a specific case of overlay between metal and contact layers of a 0.16 mm SRAM process. This layer was chosen because a significant amount of wafer contraction was observed between DI and FI, resulting in as much as 30nm of DI-FI overlay difference. The purpose of the study was to characterize the systematic DI-FI differences and gain understanding of the wafer processing parameters that affect the DI-FI differences. A designed experiment showed how certain overlay mark widths were less sensitive to processing parameters. AFM profiles of the prior-level overlay marks identified issues with mark widths 1.0um or smaller. By performing localized etches on the inner vs. outer marks of the overlay targets, it was noted that the majority of the wafer contraction was induced by etching the outer (prior level) mark. Production measurements at photo and etch showed the wafer contraction to be fairly stable over a month timeframe and independent of device and exposure tool, though large fluctuation shifts in wafer contraction were noted over a nine-month period. The methods used in this study can be helpful in understanding other DI-FI processing issues.

Overlay metrology simulations

In order to control and minimize overlay metrology errors, we have to deal with a number of design parameters both in the metrology tool domain and in the overlay target domain. For enhancing the rate of performance improvement vs. technology investment, simulation can be used for modeling both the effects of overlay metrology tool behavior and the impact of target designs on the ultimate metrology performance.

Overlay accuracy in 0.18-micron copper dual-damascene process

As overlay budgets shrink with design rules, the importance of overlay metrology accuracy increases. We have investigated the overlay accuracy of a 0.18mm design rule Copper-Dual-Damascene process by comparing the overlay metrology results at the After Develop (DI) and After Etch (FI) stages. The comparisons were done on five process layers on production wafers, while ensuring that the DI and FI measurements were always done on the same wafer. In addition, we measured the in-die overlay on one of the process layers (Poly Gate) using a CD-SEM, and compared the results to the optical overlay metrology in the scribe-line. We found that a serious limitation to in-die overlay calibration was the lack of suitable structures measurable by CD-SEM. We will present quantitative results from our comparisons, as well as a recommendation for incorporating CD-SEM-measurable structures in the chip area in future reticle designs.