Joerg Berthold

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations

A method is proposed to compensate for local delay variations by adjusting the supply voltage of individual circuit blocks. In-situ characterization of sub-blocks allows for voltage adjustment with minimum safety margin. Different strategies and circuit techniques for in-situ delay characterization of sub-blocks are described and compared. A dual VDD/power switch scheme is proposed for discrete voltage assignment to individual sub-blocks. Experimental results are presented for a test module based on an ARM9 core, fabricated in 130-nm CMOS. Yield improvement and power reduction capabilities are demonstrated by Monte Carlo simulations. For a typical setting, a reduction of 10% in power can be achieved with the proposed dual VDD/power switch concept. Using more than two supply voltages is shown to produce only small additional power savings at the price of high area overhead. The effect of the proposed scheme increases with increasing intra-die variability, which makes it suitable especially for future technologies.

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions

To meet the widely varying speed and power requirements of multifunctional mobile devices, an appropriate combination of technology features, circuit-level low-power techniques, and system architecture is implemented in a GSM/Edge baseband processor with multimedia and mixed-signal extensions. Power reduction techniques and performance requirements are derived from an analysis of relevant use cases and applications. The 44 mm2 baseband processor is fabricated in a 90-nm low-power CMOS technology with triple-well option and dual-gate oxide core devices. The ARM926 core achieves a maximum clock frequency of 380 MHz at 1.4-V supply due to the usage of thin oxide (1.6 nm) devices. Power dissipation can be adapted to the performance requirements by means of combined voltage and frequency scaling to reduce active power consumption in medium-performance mode by 68%. To reduce leakage currents during standby mode, large SRAM blocks, nFET sleep transistors, and circuit components with relaxed performance requirements are implemented using devices with 2.2-nm gate oxide thickness

Local Supply Voltage Adjustment for Low Power Parametric Yield Increase

A method is proposed to compensate for local delay variations by adjusting the supply voltage of individual circuit blocks. In-situ characterization of sub-blocks allows for voltage adjustment with minimum safety margin, and parametric yield can be increased with small energy overhead. Experimental results are presented for a test module based on an ARM9 core, fabricated in 130nm CMOS

Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies

Dual supply voltage (DSV) is a low-power design technique, which reduces the dynamic power dissipation of a digital circuit [1]. In this paper we will summarize the basic idea of this approach, its benefit and associated costs and outline the dependency of DSV on technology and device parameters. We then evaluate the use of DSV on gate level in the context of the evolving ultra deep submicron (UDSM) technology. Employing DSV exhibits a reduced leverage – especially for leakage sensitive applications – mainly due to a limited reduction of threshold voltages in UDSM technologies and due to the use of multi-threshold devices. Finally we discuss DSV design examples reported in literature and give an outlook on how their benefit is influenced by UDSM technologies.

A voltage scaling model for performance evaluation in digital CMOS circuits

We present an easy to use method to extrapolate digital circuit performance and power from nominal to worst-case operating conditions. It allows the circuit designer to explore the design space over a continuous rage of voltages and temperatures and for different process conditions. Voltage scaling is identified as a key challenge for the 22nm technology node.