Joeri De Vos

Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges

3D stacked IC (SIC) vs. 3D Interposer wafer processing and assembly challenges are discussed in this paper. We report on the key enabling technologies like wafer thinning, thin wafer handling, TSV, micro bumping, package bumping, stacking and packaging. The limited micro bump yield loss in the 3D SIC case is explained by modeling of bonding force distribution. It is also shown that for sequential stacking a NiB cap of the Cu micro bumps is heavily increasing stacking yield.

On the processing aspects of high performance hybrid backside illuminated CMOS imagers

In this paper we present a successful integration scheme of a backside (BS) illuminated 1024 × 1024 pixel, 30 µm thin, sensor array that is flip chipped on a read-out IC die with 10 µm diameter indium micro bumps, where the pixel pitch is 22.5 µm. A novel BS alignment strategy to avoid Pyrex glass as a temporary carrier for wafer thinning is described. Pyrex is namely not compatible in a high-end Si process environment due to its fragile and contaminating nature. Further special attention is given to critical steps leading toward high broadband quantum efficiency of 80–90%. It is also shown that through the introduction of high aspect ratio pixel separating trenches, inter-pixel electrical crosstalk can be avoided.

Development of multi-stack dielectric wafer bonding

We investigate multi-stack dielectric wafer bonding through two integration schemes, which provide different paths to realize vertical integration of multiple device layers. Key process steps are evaluated and optimized to enable void-less bonds at different bonding layers. Meanwhile, issues related to the wafer edge are discovered during the backside processing and the impact is analyzed. Finally, N=4 stacks are successfully demonstrated with high quality interfaces formed by dielectric bonding.

Impact of backside processing on C-V characteristics of TSV capacitors in 3D stacked IC process flows

In this paper, we describe the importance of carefully selecting the wafer backside processes in 3D stacked IC process flows. In particular, we report on the impact of TSV Via-middle reveal and backside passivation processes on the C-V characteristic of the TSV. The cause of anomalous C-V inversion of the TSV capacitor is explained and a solution is given to avoid this effect.

Hybrid backside illuminated CMOS imager for high-end applications

As compared to monolithic imagers, hybrid imagers are more costly but have more flexibility and focus typically towards high-end application like space Xray, medical diagnosis... By splitting up the processing of the detector array and the readout IC, each part can be separately optimized to the needs of the application. As such special substrates or epi layers can be chosen for introducing electrical field leading to a higher quantum efficiency (QE). Also pixel separating trenches (Figure 2) can be added for avoiding crosstalk.

Hybrid backside illuminated CMOS image sensors possessing low crosstalk

Backside illuminated (BSI) hybrid CMOS image sensors possessing excellent spectral response (> 80% between 400nm-800nm) have been previously reported by us. Particularly challenging with BSI imagers is to combine such sensitivity, with low electrical inter-pixel crosstalk (or charge-dispersion). Employing thick bulk silicon (in BSI) to maximize red response results in large crosstalk especially for blue light. In the second generation of these imagers, we undertook the exercise of solving the crosstalk problem by a two-pronged approach: a) an optimized epitaxial substrate that was engineered to maximize the internal electric field b) high aspect ratio trenches (30 μm deep) with carefully tailored sidewall passivation. The results show that the proposed optimizations are effective in curtailing crosstalk without having a major impact on other sensor parameters.