Johannes van Wingerden

Experimental verification of improved printability for litho-driven designs

The continued downscaling of the feature sizes and pitches for each new process generation increases the challenges for obtaining sufficient process control. As the dimensions approach the limits of the lithographic capabilities, new solutions for improving the printability are required. Including the design into the optimization process significantly improves the printability. The use of litho-driven designs becomes increasingly important towards the 45 nm node. The litho-driven design is applied to the active, gate, contact and metal layers. It has been shown previously, that the impact on the chip area is negligible. Simulations have indicated a significant improvement in controlling the critical dimensions of the gate layer. In this paper, we present our first results of an experimental validation of litho-driven designs printed on an immersion scanner. In our design we use a fixed pitch approach that allows to match the illumination conditions to those for the memory structures. The impact on the chip area and on the CD control will be discussed. The resulting improvement in CD control is demonstrated experimentally by comparing the experimental results of litho-driven and standard designs. A comparison with simulations will be presented.

Optimization of substrate reflectivity, resist thickness, and resist absorption for CD control and resolution

Improvement of CD control can be achieved by reduction of substrate reflectivity effects. On highly reflective substrates such as metals, dyed resists are used most of the time. Especially for poly gate level patterning, the use of Bottom Anti Reflective Coatings has become common practice. While originally organic BARCs dominated, interest is gradually shifting towards inorganic BARCs of the SiOxNy type. Their highly conformal deposition flOW really allows for tuning towards zero reflectivity, even on substrates with topography. Furthermore, the use of inorganic BARC as a hard mask for etching allows for a thinner resist layer. This reduction of the resist thickness is advantageous for obtaining high resolution. It should be realised, however, that while resist thickness reduction improves resolution, it increases CD swing effects. Also, increased resist absorption reduces CD swing, but negatively influences resolution on substrates with a low reflectivity. Thus, while resist absorption, resist thickness and substrate reflectivity can be used as parameters to optimise process performance, optimum conditions for CD control and resolution are generally different. The subject of this paper is how to determine optimum values for resist absorption, resist thickness and substrate reflection. We quantify the effect of these parameters on both CD control and resolution. Furthermore, requirements for BARC parameter variations are discussed. Finally, practical boundary conditions on increasing resist absorption a:nd thickness for better CD control are determined.Improvement of CD control can be achieved by reduction of substrate reflectivity effects. On highly reflective substrates such as metals, dyed resists are used most of the time. Especially for poly gate level patterning, the use of Bottom Anti Reflective Coatings has become common practice. While originally organic BARCs dominated, interest is gradually shifting towards inorganic BARCs of the SiOxNy type. Their highly conformal deposition now really allows for tuning towards zero reflectivity, even on substrates with topography. Furthermore, the use of inorganic BARC as a hard mask for etching allows for a thinner resist layer. This reduction of the resist thickness is advantageous for obtaining high resolution. It should be realized, however, that while resist thickness reduction improves resolution, it increases CD swing effects. Also, increased resists absorption reduces CD swing, but negatively influences resolution on substrates with a low reflectivity. THus, while resist absorption, resist thickness and substrate reflectivity can be used as parameters to optimize process performance, optimum conditions for CD control and resolution are generally different. The subject of this paper is how to determine optimum values for resist absorption, resist thickness and substrate reflection. We quantify the effect of these parameters on both CD control and resolution. Furthermore, requirements for BARC parameter variations are discussed. Finally, practical boundary conditions on increasing resist absorption and thickness for better CD control are determined.© (1999) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Lithographic process optimization using process capability analysis

A capable process fulfills many requirements on e.g. depth of focus, exposure latitude, and mask error factor. This makes a full optimization complicated. Traditionally only a few parameters are included in the optimization routine, such as the focus-dose process window, while other parameters like the (NA,σ ) illumination conditions are fixed at a specified value. In this paper we present an analytical model for describing the effect of variations in dose, focus and mask CD. We optimize the overall CD distribution, both the target value and the CD variation, taking the statistical variations of focus, dose and mask line width variations into account. The improved CD control is measured quantitatively, using the well-known process capability index (Cpk). The results are compared to traditional optimization schemes and brute force Monte Carlo simulations. Process latitudes can be better optimized while calculating the OPC curve. This is achieved by tuning the mask corrections to the process variations and simultaneously optimizing the global mask bias. Furthermore, the optimization method enables a trade off between mask error and process control. Simulated aerial image data is used to determine the optimum mask bias and illumination condition for different levels of process variation, including mask CD variation. The effect of optimizing the global mask bias is calculated. Finally, the results will be compared to experimental data for a number of illumination settings.

SPM characterizaton of anomalies in phase-shift mask and their effect on wafer features

As dimensions get smaller and circuits get more complex, the demand for comprehensive measurements of reticule geometries increases. 3D characterization of phase shift mask (PSM) is required to understand the quality of the transferred image. To avoid anomalies between the measurements, the structures on both mask/reticule and wafer should be measured using the same technique. The technique used should be insensitive to differences in the intrinsic characteristics of the materials (chromium on quartz, resist on conductive or non-conductive layers). Scanning probe microscopy (SPM) is ideally suited to make these characterizations on both masks/reticule and wafers. It quantitatively profiles lines and trenches in three dimensions. SPM is a nondestructive technique, allowing for the preservation of the integrity of mask and wafers. The profiles of features on a phase shift mask (PSM) are measured with SPM. Some undesirable effects such as micro loading versus structure size during quartz etch, positive slope of the quartz sidewall, and CD differential between chromium and quartz are characterized. Some of the corresponding features on the wafer are measured with SPM and the correlation between the mask anomalies and their effect on wafer features are established.

Bottom-ARC optimization methodology for 0.25 μm lithography and beyond

This paper reports on an optimization methodology for BARC/resist processes in order to obtain best CD-control on various substrate topographies. A selection of resist and BARC materials is studied by means of simulations and experiments. Two BARC properties, turned out to be of major importance: planarization effects on topography and etch behavior. The topography itself is very important too: step height and lateral dimensions have a severe influence on CD control. Based on a new evaluation technique, the use of topographical swing curves, the optimum thickness of the BARC layer and of the resist layer are determined.

Process, design and optical proximity correction requirements for the 65nm device generation

The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.

Evaluating design for manufacturing with process capability analysis

The shrinking of the dimensions for each new process generation increases the challenges for lithography significantly. In order to guarantee manufacturability for future process generations, a strong interaction between lithography and design is required. A quantitative measure for the manufacturability is of key importance for driving the improvements in the design for manufacturing process. Aerial image slopes or contrasts in simulated images provide a measure for the sensitivity to process variations, but do not take the statistical process variation into account. This may result in sub-optimal choices in the design for manufacturing process. This paper discusses the process capability analysis and provides an optimal design with corresponding imaging conditions, taking the statistical fluctuations of exposure dose and focus into account. The mean CD value and the CD spread are calculated as a function of the amount of variation in the process variables like focus and exposure dose. Comparing these distribution parameters to the process specifications yields the so-called process capability index as a quantitative measure for the manufacturability. Another advantage is the possibility to include the effect of mask errors on the manufacturability. Until now, however, this method had only been demonstrated for line space features. In this paper we extend the process capability analysis method for calculating the manufacturability of arbitrary layouts. The analysis is demonstrated in an evaluation of the manufacturability of various gate layer designs, both conventional as well as litho-driven re-designs.

Comparisons of 9% versus 6% transmission attenuated phase shift mask for the 65 nm device node

The minimum gate pitch for the 65 nm device node will push 193 nm lithography toward k 1 ~0.35 with numerical aperture (NA)=0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65 nm node will be difficult. Lithographers are, therefore, looking into high-transmission attenuated phase shift masks (high- T attPSMs), where T >14%, to improve process margins. The benefits of a high- T attPSM are substantial, but drawbacks like difficulty in inspection, defect free blank manufacture, and sidelobe printing may make the use of such masks impractical. One possible solution to this problem is to employ medium transmission (med- T ) attPSM, such as T = 9%, to image critical levels of the 65 nm node with 193 nm lithography. Earlier work has shown that the problems high-T attPSMs face are manageable for med- T attPSM. Sidelobe printing in particular will be treated in this work with simulation and experiment. A primary goal of this effort is to determine if the lithographic benefit of moving from industry-standard 6% attPSM to 9% attPSM is worth the risks associated with such a transition. This goal will be met through a direct comparison of experimental 0.75 NA 193 nm wavelength results for 6% versus 9% attPSM on the gate, contact/via, and metal layers at 65 nm generation target dimensions with leading edge resists.

Comparisons of 9% versus 6% transmission attenuated phase-shift mask for the 65-nm device mode

The minimum gate pitch for the 65nm device node will push 193nm lithography toward k1 ~ 0.35 with NA = 0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65nm node will be difficult. Lithographers are, therefore, looking into high-transmission attenuated phase shift mask (high-T attPSM), where T > 14%, to improve process margins. The benefits of a high-t attPSM are substantial, but drawbacks like inspection difficulty, defect free blanks manufacture, and sidelobe printing may make the use of such masks impractical. One possible solution to this problem is to employ medium transmission (med-T) attPSM, such as T = 9%, to image critical levels of the 65nm node with 193nm lithography. Earlier work shows that the problems High-T attPSMs face are manageable for med-T attPSM. Sidelobe printing in particular will be treated in this work with simulation and experiment. A primary goal of this effort is to determine if the lithographic benefit of moving from industry-standard 6% attPSM to 9% attPSM is worth the risks associated with such a transition. This goal will be met through a direct comparison of experimental 0.75NA 193nm λ results for 6% versus 9% attPSM on gate, contact/via, and metal layers at 65nm generation target dimensions with leading edge resists. Additional information on the inspectability and reticle blank manufacture of % AttPSM will also be given to provide a cohesive analysis of the transition tradeoffs.