Bryan S. Kasprowicz

Exploring new high speed mask aware RET verification flows

Lithography simulation is an integral part of semiconductor manufacturing. It is not only required in lithography process development, but also in RET design, RET verification, and process latitude analysis, from library cells to full-chip tape out. Two RET design checking flows are examined and compared. In the first flow, an image contour is simulated from post-OPC, GDSII data at best focus and exposure conditions. RET design defects are identified by comparing the calculated contours with the pre-OPC design data. To check lithography manufacturability across the typical IC process window, the second RET verification flow simulates image contours at multiple focus and exposure conditions. These RET design checking flows are implemented on new platform that combines a hardware accelerated computational engine with a new analysis method to numerically evaluate the lithographic printing and mask manufacturing challenges for a given design layout. The algorithm approach in this new system is based on image processing which is fundamentally different from conventional edge-based analysis. Specific examples of a mask aware RET verification flow leveraging this new platform and method will be provided with speed and accuracy benchmarks. Through the high speed computation of lithographic images from full chip data, many opportunities for novel and cost effective post layout lithography verification options become available. By combining the new platform with analysis steps relevant in leading edge photomask manufacturing, it may become possible to reduce the risks inherent in advanced technology tape outs while improving layout to mask fabrication cycle time and cost.

Improved prediction of across chip linewidth variation (ACLV) with photomask aerial image CD metrology

Critical dimension (CD) metrology is an important process step within the wafer fab. Knowledge of the CD values at resist level provides a reliable mechanism for the prediction of device performance. Ultimately tolerances of device electrical performance drive the wafer linewidth specifications of the lithography group. Staying within this budget is influenced mainly by the scanner settings, resist process and photomask quality. At the 65nm node the ITRS roadmap calls for sub-3nm photomask CD uniformity to support a sub-3nm wafer level CD uniformity. Meeting these targets has proven to be a challenge. What can be inferred from these specifications is that photomask level CD performance is the direct contributor to wafer level CD performance. With respect to phase shift masks, criteria such as phase and transmission control are also tightened with each technology node. A comprehensive study is presented supporting the use of photomask aerial image emulation CD metrology to predict wafer level Across Chip Linewidth Variation (ACLV). Using the aerial image can provide more accurate wafer level prediction because it inherently includes all contributors to image formation such as the physical CD, phase, transmission, sidewall angle, and other material properties. Aerial images from different photomask types were captured to provide across chip CD values. Aerial image measurements were completed using an AIMSTMfab193i with its through-pellicle data acquisition capability including the Global CDU MapTM software option for AIMSTM tools. The through-pellicle data acquisition capability is an essential prerequisite for capturing final CD data (after final clean and pellicle mounting) before the photomask ships or for re-qualification at the wafer fab. Data was also collected on these photomasks using a conventional CD-SEM metrology system with the pellicles removed. A comparison was then made to wafer prints demonstrating the benefit of using aerial image CD metrology.

Image imbalance compensation in alternating Phase-Shift Masks towards the 45nm node through-pitch imaging

The use of an Alternating Phase-Shift Mask (AltPSM) is a strong resolution enhancement technique combining high contrast and a low Mask Error Enhancement Factor with a large focus depth. However, image (or intensity) imbalance, which is intrinsically related to AltPSM imaging, is known to produce focus-dependent feature shifts. The evolution towards hyper NA immersion lithography systems and the associated shrinkage of feature sizes and pitches also puts stronger demands on the placement of the printed features, in order to meet the overlay requirements. Therefore, a good image imbalance reduction strategy is important for a successful implementation of AltPSM in manufacturing. A first step towards this implementation is to find a through-pitch imaging solution guaranteeing both the line width and line position to be within CD and overlay specifications in a sufficiently large dose-focus window. In this paper, we present a strategy to evaluate AltPSM imaging results by monitoring the edge displacement of the printed feature caused by image imbalance. The proposed method insures correct line printing within the calculated process window, taking image imbalance into account. We experimentally assess the imaging performance of a current state-of-the-art dry etched AltPSM with a nominal trench bias on a 0.85 NA immersion scanner. The results demonstrate that a through-pitch solution for printing 65 nm lines on wafer from P140 nm to isolated lines exists that meets both the CD and overlay requirements. Moreover, we have developed a methodology that effectively solves the image imbalance using a pitch-dependent trench bias in combination with an optimized etch depth, which should be chosen in accordance with the dose used for printing the 65 nm line.

Application of Chromeless Phase Lithography (CPL) masks in ArF lithography

The challenges of low k1 lithography require unique solutions at all levels of the lithography process. Chromeless phase lithography (CPL) is a promising technique that uses a 2-beam imaging strategy and a unique OPC application for enhanced CD uniformity through pitch. It is particularly effective when combined with a high numerical aperture (NA) and off-axis illumination (OAI). In addition to its imaging benefits, CPL masks offer many advantages in the manufacturing of the mask over other approaches. The manufacturing strategy and methodology employed to fabricate CPL masks will be discussed. The technical challenges of mask production will also be highlighted. Application of CPL to production ArF images were characterized through simulations and experimental data demonstrating the capability of this technique to produce complex structures.

High transmission mask technology for 45nm node imaging

The lithography prognosticator of the early 1980’s declared the end of optics for sub-0.5μm imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k1. Several authors have recently discussed manufacturing imaging solutions for sub-0.3k1 and the integration challenges. The requirements stated in the ITRS roadmap for current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will continue further for aggressive imaging solutions. Lithography and more importantly “imaging solutions” are driven by economics. The technology might be extremely innovative and “fun”, however, if its too expensive it may never see the light of scanner. The authors have investigated and compared the capability of high transmission mask technology and image process integration for the 45nm node. However, the results will be graded in terms of design, mask manufacturability, imaging performance and overall integration within a given process flow.

A practical alternating PSM modeling and OPC approach to deal with 3D mask effects for the 65nm node and beyond

Alternating PSM (Alt-PSM) has been recognized as a logical Resolution Enhancement Technique (RET) candidate for the 65nm technology node. One of the key properties this technique has to offer is high Depth of Focus (DOF) and lower Mask Error Enhancement Factor (MEEF). The so-called image imbalance is an Alt-PSM specific property which, if not dealt with correctly, constrains the added DOF. Because of mask topography, intensity differences caused by light scattering become evident between π (180°) and zero degree phase shifters. This causes a line shift that is inversely proportional to the pitch. The traditional solution of applying a fixed trench bias increases the width if the π phase shifter to level out intensities and thus minimize image imbalance. This technique may no longer be sufficient at the 65nm technology node. With the requirement to print even smaller pitches together with a tighter Critical Dimension (CD) budget, intensity imbalance is a larger concern. It may be necessary to apply a pitch dependent or variable trench bias. In this paper, we present a practical OPC modeling approach that accounts for image imbalance. The 2D modeling approach uses boundary layers to represent the 3D effect of light scattering. We demonstrate that with the boundary layer model, it is possible to predict image imbalance caused by mask 3D effects. The model can then be used either to determine the nominal trench bias or can be integrated into the OPC engine to apply a variable trench bias. Results are compared to rigorous Electro Magnetic Field (EMF) simulations and experimental exposures using an ArF scanner, targeting pitches of 130nm and above.

Tunable transmission phase mask options for 65/45nm node gate and contact processing

Today the industry is filled with intensity-balanced c:PSM and much more focus is being placed on innovative approaches such as CPL (and in conjunction with IML for Contacts) and tunable transmission embedded attenuating phase shift mask (TT-EAPSM). Each approach has its own merits and demerits depending on the manufacturing strategy and lithography performance required. Currently the only commercially available photomask blanks are different chrome thickness binary and 6% attenuating blanks using molybdenum-silicide, making the accessibility to alternate transmissions much more challenging. This paper investigates the mask manufacturability of a tunable transmission embedded attenuating phase shift mask. New film materials that are used in the mask blank manufacture are modeled, deposited and characterized to determine its ability to meet performance requirements. Sputtering models, by rate and gas component, determines film stacks with tunable transmissions and thicknesses. Chemical durability, etch selectivity and thickness are a few parameters of the films that have been characterized to enhance the manufacturability and process reliability of the masks. Lithography simulation models using measured optical properties were developed and test masks that include actual device designs were fabricated. Analysis of CD variation, pattern fidelity and process margin was performed using 3D mask simulation to understand the impact on 65nm design rules. Feasibility and performance of tunable transmission photomasks for use in design and lithography are verified. Moreover, the mask manufacturability and lithography performance is compared to other enhancement techniques and their merits presented.

The interaction of mask manufacturability and alt PSM design parameters

For the production of process generations below 100nm, double exposure alternating Phase Shift Masks (Alt.PSM) has been recognized as a proven wafer imaging technique. The large process window and relatively stable process control is seen as one of the advantages of this technology as compared with other RET approaches. The exceptional MEEF performance of the Alt. PSM is also an important factor as it makes the wafer Critical Dimension (CD) control less susceptible to CD errors on the mask. In this work a mask manufacturing simplification technique is studied and an improvement to overall manufacturability and cycle time is demonstrated through reductions in data volume and write time.

High-resolution actinic imaging and phase metrology of 193-nm CPL reticles

The recent introduction of chromeless-phase lithography (CPL) has provided lithographers with a powerful wavefront engineering tool for patterning at k1 values below 0.3. Reliable image formation at such extreme k1 requires a well-characterized CPL photomask. However, the limitations of available optical inspection tools have made the test and measurement of CPL photomasks a difficult task. In this paper, we describe preliminary imaging and phase metrology results on a leading-edge CPL reticle using an high-resolution 193-nm microscope. This microscope features a solid-state 5-kHz repetition rate, 193.4 nm actinic light source in conjunction with high-numerical-aperture (0.75 NA) optics to provide 200X magnification, 150-nm Rayleigh resolution and 35-nm pixel size over a 30-micron image field. A recently-developed phase metrology architecture facilitates optical path difference (OPD) measurements of isolated or dense features on a sub-200-nm spatial scale. We discuss the phase measurement process and present images and corresponding OPD measurements of line and contact structures on an ArF CPL reticle that is designed mainly for the 65 nm technology node. We compare these OPD measurements with predictions based on surface nano-profilometer (SNP) step-height measurements of the same feature regions.

Limits of strong phase-shift patterning for device research

Advanced transistor research requires the patterning of isolated gate feature sizes well below available illumination wavelengths. In this work, we explore the limits of imaging isolated line features using double exposure strong phase shift methods and 248 nm illumination. Fundamental issues such as aerial image size,flare, simple OPC and resist aspect ratio will be addressed. Non-lithographic feature slimming methods such as UV-bake, etch biasing and oxidation will we explored as well. It is desirable that feature slimming processing also reduce line-edge roughness. Using a combination of strong PSM imaging and feature slimming, we have developed processes for the fabrication of sub-25 nm gate features required by our Schottky Barrier transistor device development efforts.