Patrick K. Montgomery

ArF solutions for low-k 1 back-end imaging

The requirements stated in the ITRS roadmap for back-end-of-line imaging of current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will be necessary for the imaging of contacts and trenches, pushing optical lithography into the low-k1 regime. In this paper, we focus more specifically on imaging solutions for contact holes beyond the 90 nm node using high NA ArF lithography, as this is currently seen as one of the major challenges in optical lithography. We investigate the performance of various existing enhancement techniques in order to provide contact holes imaging solutions in a k1 range from 0.35 to 0.45, using the ASML PAS5500/1100 0.75NA ArF scanner installed at IMEC. For various resolution enhancement techniques (RET), the proof of concept has been demonstrated in literature. In this paper, we propose an experimental one-to-one comparison of these RET’s with fixed CD target, exposure tool, lithographic process, and metrology. A single exposure through pitch (dense through isolated) printing solution is preferred and is the largest challenge. The common approach using a 6% attenuated phase-shifted mask (attPSM) with a conventional illumination fails. The advantages and drawbacks of other techniques are discussed. High transmission (17%) attenuated phase shift, potentially beneficial for part of the pitch range, requires conflicting trade-offs when looking for a single exposure through pitch solution. More promising results are obtained combining a BIM or a 6% attPSM with assist slots and off-axis illumination, yielding a depth of focus (DOF) at 8% exposure latitude (EL) greater than 0.31 μm from 200 nm pitch through isolated. Chromeless phase lithography (CPL) is also discussed with promising results obtained at the densest pitch. At a 0.4 k1, an experimental extrapolation to 0.85NA demonstrates that a pitch of 180 nm can be resolved with 0.4 μm DOF at 8% EL. For all of these imaging solutions, various metrics are studied to compare printing performance. In addition to process latitude, we consider forbidden pitches, sidelobes printability, and mask error enhancement factor (MEEF).

Resist reflow for 193-nm low-K1 lithography contacts

Contact patterning for advanced lithography generations is increasingly being viewed as a major threat to the continuation of Moores Law. There are no easy patterning strategies which enable dense through isolated contacts of very small size. Lack of isolated contact focus latitude, high dense contact mask error factor and incredibly low defectivity rate requirements are severe issues to overcome. These difficulties mean that new and complex patterning methods for contacts at the 90nm and 65nm device generations are being considered. One possible option for improving the process window of contact patterning is resist reflow. Resist reflow can supplement almost any other optical extension method for contact lithography. Previous results have shown the significant benefits of this method for CD control on semi-dense and isolated contact for the 100nm device generation. This work extends the previous work by investigating very dense pitch through isolated contact patterning at 193nm low K1 lithography regimes. The encouraging overall CD control and process window of reflowed contacts using the ARCH TIS2000 bilayer resist system is analyzed through pitch for different imaging options. An investigation of the capability of resist reflow in combination with optimized reticle and illumination for the 65nm device generation is also presented as are details of defectivity levels for reflowed contacts on 90nm device products.

Process, design and optical proximity correction requirements for the 65nm device generation

The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.

High-NA ArF lithography for 70-nm technologies

Complementary phase shift mask (c:PSM) is one of the most promising resolution enhancement techniques (RET) to extend low k1 optical lithography. Nonetheless binary intensity mask (BIM) imaged with 193 nm wavelength at high numerical aperture (0.75) off-axis illumination (OAI) might still be used for nested through isolated feature sizes as small as 70 nm. We compare the feasibility of using c:PSM and BIM for 70nm generation technologies. Experimental results of high NA imaged BIM and c:PSM are presented.

CPL mask technology for sub-100-nm contact hole imaging

Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/- 9nm1. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error factor (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as contacts. We have investigated the use of CPL mask technology for ArF contact hole imaging for sub-100nm contact imaging. The authors activities have been focused on the design, fabrication and integration of imaging technology. In this paper the authors emphasis will be on issues related to pattern layout, mask fabrication and image processing.

Defect printability in CPL mask technology

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CPL) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. These new reticle technologies have many issues that are similar to simple binary masks. The authors have investigated the printability of defects in CPL mask technology. Programmed defects of various sizes and types have been simulated and printed for sub 100nm imaging. High resolution scanning electron microscopy has been used to characterize these defects and develop an understanding of size and type that prints. In this paper the authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds.

The impact of MEEF through pitch for 120-nm contact holes

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometries has forced device manufacturers to k1’s approaching 0.40. In this paper the authors will focus on the impact of mask exposure error factor (MEEF) through pitch for 120nm contacts with and without assist features. Experimental results show that although the addition of scatter bars improves depth of focus it has a negative effect on MEEF.

Comparisons of 9% versus 6% transmission attenuated phase shift mask for the 65 nm device node

The minimum gate pitch for the 65 nm device node will push 193 nm lithography toward k 1 ~0.35 with numerical aperture (NA)=0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65 nm node will be difficult. Lithographers are, therefore, looking into high-transmission attenuated phase shift masks (high- T attPSMs), where T >14%, to improve process margins. The benefits of a high- T attPSM are substantial, but drawbacks like difficulty in inspection, defect free blank manufacture, and sidelobe printing may make the use of such masks impractical. One possible solution to this problem is to employ medium transmission (med- T ) attPSM, such as T = 9%, to image critical levels of the 65 nm node with 193 nm lithography. Earlier work has shown that the problems high-T attPSMs face are manageable for med- T attPSM. Sidelobe printing in particular will be treated in this work with simulation and experiment. A primary goal of this effort is to determine if the lithographic benefit of moving from industry-standard 6% attPSM to 9% attPSM is worth the risks associated with such a transition. This goal will be met through a direct comparison of experimental 0.75 NA 193 nm wavelength results for 6% versus 9% attPSM on the gate, contact/via, and metal layers at 65 nm generation target dimensions with leading edge resists.

Imaging techniques to support low k1 optical lithography

Summary form only given. With half pitch k factors rapidly approaching sub 0.4, many lithography groups have looked seriously into alternative patterning and mask techniques. The semiconductor industry continues to explore numerous techniques for printing smaller geometrys with the hope of improving resolution and process window. There are a number of new and interesting mask/illumination techniques that have been published. These new mask techniques come with a variety of integration issues and manufacturing risks. The ITRS roadmap has become a living document with continuous change as imaging nodes change with improvements in imaging techniques or from delays in tool and process programs. ArF initially was planned for introduction at 0.18 /spl mu/m, however; real implementation may not begin until the 0.13 /spl mu/m or 0.100 /spl mu/m depending on the company. Moreover, very high NA ArF is now considered the up front candidate for the 0.065 /spl mu/m node. This presentation will discuss the various activities centered on imaging techniques to support the 0.065/spl mu/m node with high NA ArF. The authors will discuss experimental activities for 0.100 /spl mu/m and sub-0.100 /spl mu/m contacts along with 0.065mn imaging through a variety of mask and illumination techniques.

Model-based design improvements for the 100-nm lithography generation

Due to the challenging design rule and CD control requirements of the 100 nm device generation, a large number of complex patterning techniques are likely to be used for random logic devices. The complexity of these techniques places considerable strain upon model-based OPC software to identify and compensate for a wide range of printing non- idealities. Additionally, the rapidly increasing cost of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have evaluated the capability of leading edge model-based OPC software to meet the challenging lithography needs of the 100 nm device generation. Specifically, we have implemented and verified model usefulness to correct for pattern deformation in complex binary gate, contact and via processes utilizing highly optimized illumination. Additionally, we present results showing the abilities of model-based methods to accurately find design related printing problems in complementary phase shift gate designs before they are committed to an expensive reticle.