John Chern

A 25–75 GHz Broadband Gilbert-Cell Mixer Using 90-nm CMOS Technology

A compact and broadband 25-75-GHz fully integrated double-balance Gilbert-cell mixer using 90-nm standard mixed-signal/radio frequency (RF) CMOS technology is presented in this letter. A broadband matching network, LC ladder, for Gilbert-cell mixer transconductance stage design is introduced to achieve the flatness of conversion gain and good RF port impedance match over broad bandwidth. This Gilbert-cell mixer exhibits 3plusmn2dB measured conversion gain (to 50-Omega load) from 25 to 75GHz with a compact chip size of 0.30mm2. The OP1 dB of the mixer is 1dBm and -4dBm at 40 and 60GHz, respectively. To the best of our knowledge, this monolithic microwave integrated circuit is the highest frequency CMOS Gilbert-cell mixer to date

Design and analysis of CMOS broad-band compact high-linearity modulators for gigabit microwave/millimeter-wave applications

CMOS broad-band compact high-linearity binary phase-shift keying (BPSK) and IQ modulators are proposed and analyzed in this paper. The modulators are constructed utilizing a modified reflection-type topology with the transmission lines implemented on the thick SiO/sub 2/ layer to avoid the lossy silicon substrate. The monolithic microwave integrated circuit (MMIC) chips were fabricated using standard bulk 0.13-/spl mu/m MS/RF CMOS process and demonstrated an ultracompact layout with more than 80% chip size reduction. The broadside couplers and 180/spl deg/ hybrid for the modulators in the CMOS process are broad-band designs with low phase/amplitude errors. The dc offset and imbalance for the proposed topology are investigated and compared with the conventional reflection-type modulators. The measured dc offset was improved by more than 10 dB. Both BPSK and IQ modulators feature a conversion loss of 13 dB, a modulation bandwidth of wider than 1 GHz, and second- and third-order spur suppressions of better than -30 dBc. The IQ modulator shows good sideband suppression with high local-oscillator suppression from 20 to 40 GHz. The modulators are also evaluated with a digital modulation signal and demonstrate excellent modulator quality and adjacent channel power ratio.

A 50 to 94-GHz CMOS SPDT Switch Using Traveling-Wave Concept

A fully integrated single-pole-double-throw transmit/receive switch has been designed and fabricated in standard bulk 90-nm complementary metal-oxide semiconductor (CMOS) technology. Traveling wave concept was used to minimize the insertion loss at higher frequency and widen the operating bandwidth. The switch exhibits a measured insertion loss of 2.7 -dB, an input 1-dB compression point (input P1 dB) of 15 dBm, and a 29-dB isolation at the center frequency of 77 GHz. The total chip size is only 0.57 times 0.42 mm 2 including all testing pads. To our knowledge, this is the first CMOS switch demonstrated beyond 50 GHz, and the performances rival those monolithic microwave integrated circuit switches using standard GaAs PHEMTs

A miniature 25-GHz 9-dB CMOS cascaded single-stage distributed amplifier

A 25-GHz complementary metal oxide semiconductor (CMOS) cascaded single-stage distributed amplifier (CSSDA) using standard 0.18-/spl mu/m CMOS technology is presented in this letter. It demonstrates the highest gain-bandwidth product (GBP) with smallest chip area reported for a fully-integrated CMOS wideband amplifier using a standard Si-based integrated circuit process. The chip size including testing pads is only 0.36mm/sup 2/, and the ratio of GBP to chip size achieves 552GHz/mm/sup 2/. This circuit is the first CSSDA realized in CMOS technology, and represents state-of-the-art performances.

A Fundamental 90-GHz CMOS VCO Using New Ring-Coupled Quad

A new circuit topology, named ring-coupled quad for millimeter-wave voltage controlled oscillator (VCO) design, is proposed. The proposed circuit topology provides higher open loop voltage gain than conventional cross-coupled pair. The layout of the proposed ring-coupled quad is fully symmetric without additional interconnection lines. A 90-GHz VCO using 90-nm CMOS process is implemented with this ring-coupled quad. This 90-GHz oscillator demonstrates a 2.5-GHz tuning range and higher than -20dBm output power. The proposed ring-coupled quad is suitable for the realization of high frequency VCOs

A harmonic injection-locked frequency divider in 0.18-/spl mu/m SiGe BiCMOS

A harmonic injection-locked frequency divider for high-speed applications is presented in this letter. In order to enhance the bandwidth of the high-order frequency division, a positive feedback is employed in the design of the subharmonic mixer loop. The proposed circuit is implemented in a 0.18-mum SiGe BiCMOS process. With a singled-ended super-harmonic input injection of 0dBm, the frequency divider exhibits a locking range of 350MHz (from 59.77 to 60.12GHz) for the divide-by-four frequency division while maintaining an output power of -16.6plusmn 0.5dBm within the entire frequency range. The frequency divider core consumes a dc power of 50mW from a 3.6-V supply voltage

A compact 35-65 GHz up-conversion mixer with integrated broadband transformers in 0.18-/spl mu/m SiGe BiCMOS technology

This paper presents a compact 35-65 GHz Gilbert cell up-convert mixer implemented in TSMC 0.18-mum SiGe BiCMOS technology. Integrated broadband transformers and meandered thin-film microstrip lines were utilized to achieve a miniature chip area of 0.6 mm times 0.45 mm. The compact MMIC has a flat measured conversion loss of 7 plusmn 1.5 dB and LO suppression of more than 40 dB at the RF port from 35 to 65 GHz. The power consumption is 14 mW from a 4-V supply. This is a fully integrated millimeter-wave active mixer that has the smallest chip area ever reported, and also the highest operation frequency among up-conversion mixers using silicon-based technology

A 60GHz transmitter with integrated antenna in 0.18/spl mu/m SiGe BiCMOS technology

A 60GHz SiGe HBT transmitter IC with integrated antenna in a standard-bulk 0.18mum SiGe BiCMOS process is reported. This chip is composed of a VCO, a sub-harmonic mixer, a PA, and a tapered-slot antenna, all with differential designs. The measured results show 15.8dBm output power and 20.2dB conversion gain with 281mWdc power consumption

An Experimental Study on High-Frequency Substrate Noise Isolation in BiCMOS Technology

In this letter, four substrate noise isolation structures in standard 0.18-mum SiGe bipolar CMOS technology were investigated using S-parameter measurements. The experimental and simulated results on different isolation structures, such as triple-well p-n junction isolated walls, deep trench isolation, and double P+ guard-ring structures, are presented. Each element in the equivalent circuits has been calculated or fitted based on the parasitic resistance, capacitance, and physical dimensions using the device simulator MEDICI and the measured results of the test patterns. The proposed structure B significantly reduced substrate noise below -70 dB up to 20 GHz. The proposed structure C with an extra triple-well junction achieved the best isolation at the lower frequency range, in which |S21| was less than -71 dB from 50 MHz to 10.05 GHz, and -56 dB from 10.05 to 20.05 GHz. The measured results showed an excellent agreement with the calculations. Structure B is good enough and is recommended for a general-purpose RF circuit design, whereas structure C can be used in a highly sensitive RF circuit block below 10 GHz.

Geometry Effect on SiGe Heterojunction Bipolar Transistor Unit Cell for 1 W High-Efficiency RF Power Amplifier Applications

The effect of geometry on the RF power performance of silicon–germanium heterojunction bipolar transistor (SiGe HBT) unit cells is investigated using various emitter finger spacing (S). Two unit cells, namely, HBT-1 and HBT-2 with the same emitter area of 8×0.6×10 µm3 but with different S values are thoroughly discussed. The S values of HBT-1 and an HBT-2 are 2 and 5 µm, respectively. The obtained measurements, including DC characteristics and small- and large-signal performance characteristics of high-breakdown SiGe HBT unit cells, are presented. The HBT-1 in class-AB operations at 2.4 GHz achieves an output 1 dB compression point (OP1dB) of 16.0 dBm, a maximum output power of 17.4 dBm, and a peak-power added efficiency (PAE) of 59.1%. Under the same testing conditions, HBT-2 achieves an OP1dB of 19.6 dBm, a maximum output power of 20.6 dBm, and a PAE of 64.5%. HBT-2 yields significant improvements in all power performance parameters compared with HBT-1, such as 3.6 dB in an OP1dB, a maximum output power of 3.2 dB, a PAE of 5.4%, and an improvement in the power performance figure of merit (FOM) of approximately 50%, which is attributed to the fact that HBT-2 has a lower thermal effect than HBT-1. The thermal effect affects both DC and output power characteristics. A 1 W power device fabricated by combining eight HBT-2 unit cells achieves a power gain of 14.5 dB and a maximum PAE (PAEmax) of 75% in a class-AB operation at 2.4 GHz. The power density is calculated to be up to 2.6 mW/µm2. These results demonstrate that SiGe HBT technology has great potential for high-power amplifier applications.