Mehmet Soyuer

Integrated RF components in a SiGe bipolar technology

Several components for the design of monolithic RF transceivers on silicon substrates are presented and discussed. They are integrated in a manufacturable analog SiGe bipolar technology without any significant process alterations. Spiral inductors have inductance values in the range of /spl sim/0.15-80 nH with typical maximum quality-factors (Q/sub max/) of 3-20. The Q/sub max/s are highest if the doping concentration under the inductors is kept minimum. It is shown that the inductor area is an important parameter toward optimization of Q/sub max/ at a given frequency. The inductors can be represented in circuit design by a simple lumped-element model. MOS capacitors have Qs of /spl sim/20/f (GHz)/C(pF), metal-insulator-metal (MIM) capacitors reach Qs of /spl sim/80/f (GHz)/C(pF), and varactors with a 40% tuning range have Qs of /spl sim/70/f (GHz)/C(pF). Those devices can he modeled by using lumped elements as well. The accuracy of the modeling is verified by comparing the simulated and the measured high-frequency characteristics of a fully integrated, passive-element bandpass filter.

A fully-monolithic SiGe differential voltage-controlled oscillator for 5 GHz wireless applications

A fully integrated and differential SiGe VCO was designed for 5 GHz wireless applications. The measured phase noise is -98 dBc/Hz at 100 kHz offset off the 5 GHz carrier. It has a tuning range of 12.3% with a control voltage from 0 to 3 V, and a figure of merit of more than -180 dBc/Hz, The current drawn from 3 V is 5 mA for the core and 2.2 mA for the output buffers.

Frequency limitations of a conventional phase-frequency detector

The phase and frequency discriminator characteristics of a digital phase-frequency detector (DPFD) are analyzed in detail. Analytical expressions that correctly predict the high-frequency behavior of the circuit are derived. The results show excellent agreement with measurements and computer simulations. >

SiGe power HBT's for low-voltage, high-performance RF applications

Silicon-Germanium (SiGe) power heterojunction bipolar transistors (HBTs) are fabricated by using two or ten device unit cells with an emitter area of 5/spl times/0.5/spl times/16.5 /spl mu/m/sup 2/ each. The large power transistor features 1 W RF output power at 3-dB gain compression, 3.5 V bias, and 2.4 GHz with a maximum power-added-efficiency (PAE) of 48% for class A/B operation. At a supply voltage of 1.5 V, the transistor delivers a 3-dB RF output power of 150 mW with a PAE of 47%. It is shown that a high collector doping level is advantageous for low-voltage operation. Further, by using special bias sense ports, the interconnect losses are found to degrade the device performance to a considerable degree.

Single chip 4/spl times/500 Mbaud CMOS transceiver

This CMOS chip replaces a 72-wire interface with 4 serial, duplex links, for relief of interconnect congestion in applications such as large switching systems. The design supports transmission at 1.6 Gb/s per direction in full-duplex mode and provides the user with a transparent interface. The data source provides fixed-length synchronous packets segmented into 4 parallel bytes along with parity and flag bits. The packet size can be programmed up to 4/spl times/64 B with a parameter loaded from an external controller. Data packets can he transmitted contiguously. During idle periods that are marked by a flag, the circuit generates and transmits fill packets, which start with a non-data Comma character. The Comma marks both byte and packet boundaries on a serial link. The Fill packets carry an idle sequence or diagnostic and control information such as Not Operational, Remote Wrap, or Unwrap. Each link carries 400 Mb/s, corresponding to 500 Mbaud after 8 B/10 B encoding.

High-frequency phase-locked loops in monolithic bipolar technology

Circuit design techniques for realizing high-frequency, low-power phase-locked loops (PLLs) in monolithic silicon bipolar technology are discussed. A varactor-tuned voltage-controlled oscillator (VCO), an analog phase detector, and a bandgap reference have been utilized as building blocks. A test circuit fabricated in a 2- mu m bipolar process exhibited a maximum center frequency of 350 MHz, and the PLL pull-in range was larger than +or-1%. The circuit operates from a 5-V supply and dissipates 270 mW. >

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop

A 10 Gb/s clock and data recovery (CDR) circuit and a 1:4 DMUX are implemented in 0.12 /spl mu/m CMOS. The CDR employs a secondary wideband delay-locked loop (DLL) to enable independent bandwidth control for jitter transfer and jitter tolerance. The proposed clock recovery and data recovery (CRDR) system enhances the jitter tolerance at high frequencies and offers less data-pattern-dependency for CDRs that use a binary phase detector.

A 350 MHz bipolar monolithic PLL

A high-frequency, low bipolar monolithic phase-locked loop which can be used in clock recovery systems operative above 300 MHz has been designed and fabricated. Building blocks of the phase-locked-loop (PLL) circuit to be discussed include an analog phase detector, a temperature-compensated VCO (voltage-controlled oscillator) with an on-chip varactor diode, a two-stage loop amplifier, and a bandgap reference. The circuit operates from a 5-V supply and dissipates 270 mW.<<ETX>>