John H. Zhang

Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts

Self-aligned gate-first VFETs using a gate spacer recess

Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device

Methods of forming vertical transistor devices with self-aligned replacement gate structures

New CMP processes development and challenges for 7nm and beyond

Methods of simultaneously forming bottom and top spacers on a vertical transistor device

METHODS OF FORMING A GATE STRUCTURE ON A VERTICAL TRANSISTOR DEVICE

Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI

Method of forming self-aligned metal lines and vias

Static discharger for integrated circuit, and diode array