Chanro Park

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Fabrication of 28nm pitch Si fins with DSA lithography

Directed Self-Assembly (DSA), as an extension of current state-of-the-art photolithography, has demonstrated the capability for patterning with resolution and cost effectiveness beyond the capability of other techniques. Previous studies of DSA have reported encouraging benchmarks in defect density and throughput capability for the patterning step, and such results provide a foundation for our ongoing efforts to integrate the DSA patterning step into a robust process for fabricating device layers. Here we provide a status report on the integration of two chemoepitaxy DSA patterning methods for the fabrication of 28nm pitch Si fin arrays. In addition to the requirements for a robust pattern transfer process, it is also important to understand the pattern design limitations that are associated with DSA. We discuss some of the challenges and opportunities associated with developing efficient device designs that take advantage of the capabilities of DSA.

E-beam inspection of EUV mask defects: To etch or not to etch?

EUV Lithography is aimed to be inserted into mainstream production for sub-20nm pattern fabrication. Unlike conventional optical lithography, frequent defectivity monitors (adders, repeaters etc.) are required in EUV lithography. Due to sub-20nm pattern and defect dimensions e-beam inspection of critical pattern areas is essential for yield monitor. In previous work we showed sub-10nm defect detection sensitivity1 on patterned resist wafers. In this work we report 8-10× improvement in scan rates of etched patterns compared to resist patterns without loss in defect detection sensitivity. We observed good etch transfer of sub-10nm resist features. A combination of smart scan strategies with improved etched pattern scan rates can further improve throughput of e-beam inspection. An EUV programmed defect mask with Line/Space, Contact patterns was used to evaluate printability of defects and defect detection (Die-Die and Die-Database) capability of the e-beam inspection tool. Defect inspection tool parameters such as averaging, threshold value were varied to assess its detection capability and were compared to previously obtained results on resist patterns.

Air spacer for 10nm FinFET CMOS and beyond

For the first time, we report integration of air spacers with FinFET technology at 10nm node dimensions. The benefit of parasitic capacitance reduction by air spacers has been successfully demonstrated both at transistor level (15–25% reduction in overlap capacitance (COT)) and at ring oscillator level (10–15% reduction in effective capacitance (Cf)). Key process challenges and device implications of integrating air spacers in FinFET are identified. We propose a partial air spacer scheme, in which air spacers are formed only above fin top and sandwiched by two dielectric liners, as a viable option to adopt air spacers in FinFET technology with minimal risks to yield and reliability.