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Dive into the research topics where Mark D. Hall is active.

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Featured researches published by Mark D. Hall.


international soi conference | 2007

Characteristic Study of SOI eSiGe Techonology

Da Zhang; Laegu Kang; D. Goedeke; A. Nagy; Veeraraghavan Dhandapani; J. Hildreth; C.C. Fu; T. Kropewnicki; Mohamad M. Jahanbani; H. Martinez; R. Noble; D. Eades; Bich-Yen Nguyen; Venkat R. Kolagunta; Mark D. Hall; J. Cheek; S. Venkatesan

This paper presents a detailed study of SOI source/drain embedded SiGe (eSiGe) technology with a focus on parasitic characteristics. It shows that eSiGe can appreciably suppress on-state floating body effect and improve device exterior resistance. Although eSiGe only physically addresses P-FET, junction capacitances of both P- and N-FETs can be impacted.


Archive | 2006

Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility

Mehul D. Shroff; Paul A. Grudowski; Mark D. Hall; Tab A. Stephens


Archive | 2011

Non-volatile memory and logic circuit process integration

Mehul D. Shroff; Mark D. Hall


Archive | 2013

Non-volatile memory (NVM) and logic integration

Mark D. Hall; Frank K. Baker; Mehul D. Shroff


Archive | 2006

Method for forming a stressor structure

Mark D. Hall; Rode R. Mora; Michael D. Turner; Laegu Kang; Toni D. Van Gompel; Stanley M. Filipiak


Archive | 2013

Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic

Mark D. Hall; Mehul D. Shroff; Frank K. Baker


Archive | 2006

STI stressor integration for minimal phosphoric exposure and divot-free topography

Mark D. Hall; Peter J. Beckage; John J. Hackenberg; Toni D. Van Gompel


Archive | 2013

Logic transistor and non-volatile memory cell integration

Mark D. Hall; Mehul D. Shroff


Archive | 2011

LOGIC AND NON-VOLATILE MEMORY (NVM) INTEGRATION

Mehul D. Shroff; Mark D. Hall


Archive | 2014

Method of making a logic transistor and non-volatile memory (NVM) cell

Mehul D. Shroff; Mark D. Hall

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