Daniel Tekleab

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.

Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High-

Achieving low p-channel metal-oxide-semiconductor (PMOS) threshold voltages with metal gates and high-k dielectrics is challenging with conventional gate-first complimentary metal-oxide-semiconductor process integration. This study, for the first time, explores the tradeoffs in using different combinations of thin-strained Si1 - x Gex channels, boron counterdopings, Si capping layers, and different metal-gate electrodes to obtain low PMOS threshold voltages with metal gate on high-k dielectrics in a gate-first integration technology. Device simulations are used to explain the experimental threshold voltage trends with varying Si1 - x Gex thicknesses, boron counterdopings, and gate work functions.

k

Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during the physical deposition process. Only the multi-layer model is able to simultaneously match the experimental data on drive current vs. etch-stop layer stress, poly pitch, source/drain recess, and spacer stress

Dielectrics

We develop, for the first time, a compact and scalable model to account for the poly-space effects (PSEs) in uniaxially-strained etch stop layer (ESL) stressors. The model is based on 2-dimensional (2D) finite element (FEM) stress simulations and 4-point bending characterization of silicon, and agrees well with measured data. The impact of PSEs on circuit performance is also discussed.

Multi-Layer Model for Stressor Film Deposition

In this paper we investigate state-of-the-art undoped channel FinFETs and FinDiodes with an emphasis on I/O and ESD applicability. Utilizing electrical characterization data, 3D TCAD, and a compact model, we demonstrate that FinFETs and FinDiodes exhibit a very appealing combination of high breakdown voltage and low Ioff for I/O and ESD protection circuit applications.

Modeling and Simulation of Poly-Space Effects in Uniaxially-Strained Etch Stop Layer Stressors

We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (Csub) epitaxial Si:C and laser spike annealing (LSA) for increased Csub incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% Csub and 60% Rch reduction for 2.2% Csub are demonstrated.

Study of undoped channel FinFETs in active rail clamp ESD networks

We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The optimization takes into account the 1-D and 2-D geometry effects, including poly-pitch, and is in good agreement with stress simulations

An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing

Optimization of post nitridation annealing (PNA) in plasma nitrided gate oxide integration exhibited reduction of gate leakage current and improvement of negative bias temperature instability (NBTI) without drive current loss have been demonstrated. An improved interface quality by a high temperature or a high pressure O2 PNA is the main factor to improve channel mobility. The addition of both post clean annealing (PCA) and post oxidation annealing (POA) allows for gate dielectric scaling down with the benefit of drive current improvement. An increase in oxide thickness and a decrease in relative nitrogen concentration resulted in the improvement of NBTI characteristics.

Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors

Using PMOSFETs with a range of built-in process induced stress and four-point bending characterization, we present evidence that the stress response of PMOSFETs increases with channel stress. A novel method incorporating the characterization data with channel stress simulation has been developed which shows excellent agreement between our prediction and measured transistor performance data for nitride etch stop layer splits. Our analysis indicates that PMOSFETs will continue to show increasingly effective performance enhancement at higher channel stress

Optimization of annealing process of pulsed RF decoupled plasma nitridation oxynitrides

First functional 45 nm SGOI CMOS devices on bonded SGOI substrates with T/sub SOI/<45 nm exhibited superior short-channel control and comparable reliability to SOI devices. A 67% Gm enhancement was observed in long-channel nMOS SGOI devices, 18% drive current increase for short-channel SGOI devices, and 12% faster ring-oscillators were exhibited with respect to control SOI devices. Functional SRAM bit cells down to V/sub dd/=0.9 V were also demonstrated.