Chris A. Spence

Integration of optical proximity correction strategies in strong phase shifters design for poly-gate layers

In this paper we discuss some of the problems and solutions discovered when implementing 2-mask strong phase shifter designs for the poly gate level in logic designs. Experimental results are presented showing pattern fidelity for different reticle designs. Simulations are presented indicating the improvement in pattern fidelity that can be expected from using OPC. Simulations, PSM assignment and model-based OPC correction are performed by the Calibre WORKbench, Calibre DRC, Calibre PSMgate and Calibre OPCpro tools from Mentor Graphics. In conclusion, we show that while fairly simple designs can be used to achieve 250 nm design rules (approximately 150 nm gates), in order to achieve both pattern fidelity as well as small feature size it is necessary to use 3-layer/phase-aware model-based OPC to correct for pattern distortion for design rules of 180 nm and below (approximately 100 nm phase-shifted gates).

Phase shifting and optical proximity corrections to improve CD control on logic devices in manufacturing for sub-0.35-um i-line

The use of I-Line exposure wavelength for manufacturing at and beyond 0.35 micrometers presents many challenges in manufacturing. The lack of resolution, depth of focus, exposure latitude, and iso/dense offsets have caused some to switch from I-Line to DUV. With our installed I-Line base we felt it necessary to implement techniques to extend our tool life, reduce manufacturing costs while improving manufacturing margins. The results of the differential modification techniques were used to reduce the effects of topography, density, and low k lens issues. The differences seen between the binary and phase shift plates show the advantage of phase shifting below 0.35 (mu) manufacturing. We have been able to demonstrate between critical dimension (CD) control using phase shift mask with dense iso compensation over a standard binary reticle. The data shows improved CD control across the stepper field, wafer, and overall lot distribution. The impact of this work was improved speed performance. It also allowed us to move the CDs to smaller dimension because of the better control without increasing fallout due to electrical parametric roll-off.

Impact of coma on CD control for multiphase PSM designs

Alternating PSM applied selectively to transistor regions on the poly gate mask is one way to achieve smaller gate CDs and tighter CD control. When using multiphase PSMs we have observed, experimentally, a difference between the CDs of isolated lines when the phase shifter is on the right side compared to the left side (we have called this effect the PSM right-left effect). The effect is shown to correlate with lens coma and the magnitude of the effect is also a strong function of defocus. In this paper we present experimental data showing the magnitude of the effect and how it can be minimized by choosing optimum values of numerical aperture (NA) and partial coherence ((sigma) ). The magnitude of the effect within the stepper field is shown to correlate with measured coma values. The sensitivity of the effect to defocus was calculated. Aerial Image simulation was performed and found to predict the experimental behavior to within a factor of two. Variations in PSM design were explored using simulation. In general, the effect is reduced if the PSM layout is symmetrical. By comparing the sensitivity to coma of various PSM designs with the sensitivity of line pair structures on binary masks we were able to determine which designs had acceptable coma sensitivity.

Full-chip lithography simulation and design analysis : How OPC is changing IC design

Ten years ago Model-Based OPC (MB-OPC) was a research project of questionable usefulness, seen possibly as a fix until the next generation stepper was available. Today MB-OPC is one of the key technologies enabling 90nm production. In that brief span many technological challenges were resolved to allow MB-OPC to be performed on full chip layout with manageable computer resources and turnaround times. As MB-OPC has transitioned from a research to a production activity, several organizational challenges have arisen. Defining the steps and procedures involved in creating OPC techfiles has been necessary to allow the increased workload to be shared. Testing and documenting the OPC recipes has become a necessary discipline to ensure quality and repeatability in manufacturing. In addition to the engineers who create the OPC recipes, we now also have Fab OPC Engineers to support OPC verification and continuous improvement activities. Furthermore, the OPC process, i.e. the modification of the layout to account for the manufacturing process, has provided a tantalizing link between the design, process development and yield engineering communities. The EDA framework appears to provide a common language, however we are just beginning to ask the right questions to allow us to unlock the potential that appears so close. The paper will begin with a historical overview of the development of MB-OPC and describe the seemingly overwhelming obstacles, both computational and in mask fabrication that had to be overcome. The second part of the paper will deal with some of the problems that have arisen as MB-OPC has become a critical technology for high volume production. The final part of the paper will discuss how MB-OPC has changed the way that Lithography, Integration and Design engineers interact. Some examples of design/process interaction will be given as well as a discussion of future developments.

Large-area optical design rule checker for logic PSM application

An aerial optical design rule checker (ODRC) that will handle large areas is used to validate the automatic CAD software used for application of alternating Phase Shift Mask technology to logic devices. An automatic alternating aperture layout algorithm developed internally by Advanced Micro Devices is applied to 0.24 to 0.50 micrometers electrical designs. The layout is then verified for different stepper and defocus values by the ODRC which utilizes the simulated aerial image to compare directly to the electrical design database. Entire databases are handled by fracturing the database into optically isolated areas or by using a sliding window technique. Small areas up to 420 um per side can be done with single processor workstations with at least 512 megabyte of memory. Larger problems require multiprocessor computers with at least 16 gigabyte of memory. Full circuit analysis should be done on systems with at least 64 gigabyte of memory in order to accomplish solving the problem in a reasonable time frame.

Impact of optical enhancement techniques on the mask error enhancement function (MEEF)

Resolution, R, in optical lithography is often described by the Rayleigh equation: R equals k1(lambda) /NA. Since the 0.25 um generation there has been a trend of aggressive gate length reduction for high performance devices. Leading edge logic technologies require gate CDs equal to ½to 2/3 the wavelength of the exposure system. Even with high NA steppers and scanners low k1 patterning is a requirement. Development of processes utilizing OPC and PSM technology is critical to achieving adequate process latitude and CD control. As k1 factor falls below 0.5 the image quality and contrast degrades substantially. One result of low contrast images is that the CD variation in the photomask gives rise to larger than expected printed CD changes: the so-called MEEF. The MEEF can be simply defined as the ratio of the change of the resist feature width to the change in the mask feature width, assuming constant process and illumination conditions. For a 4x mask the MEEF can be calculated.

Automatic defect severity scoring for 193-nm reticle defect inspection

Sub-wavelength lithography requires knowledgeable application of resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and phase shift mask (PSM). Use of RETs, in turn, requires that new photomask specifications and special requirements for mask defect printability be taken into consideration. This is especially true, as the photomasks critical dimensions become more aggressive (400 nm moving toward 300 nm). Traditionally, mask defect analysis and subsequent defect disposition has been accomplished by first performing automated reticle inspection, and then by visual inspection ultimately dependent on operator judgement. As the semiconductor industry moves to more challenging process generations this methodology is no longer viable for assessing the impact of a defect on the printed wafer. New techniques for more accurate, production-worthy defect printability analysis and defect disposition procedures are required. Developed at Numerical Technologies, Inc. is the Virtual StepperTM System that offers a fast, accurate software solution for defect printability analysis based on state-of- the-art lithography simulation techniques for advanced masks production using OPC and PSM. The newly developed Virtual Stepper System feature, Automatic Defect Severity Scoring (ADSS) provides fully automated and accurate defect impact analysis capability by calculating a consistent Defect Severity Score (DSS) for each defect detected by an inspection tool. DSS is an overall score that quantifies the impact of a given defect on surrounding features and can be used as a comprehensive indicator of defect printability. Taken into consideration, are not only printing defects, but defects which cause critical dimension (CD) errors altering a given process window.

Comparison of binary mask defect printability analysis using virtual stepper system and aerial image microscope system

As advanced process technologies in the wafer fabs push the patterning processes toward lower k1 factor for sub-wavelength resolution printing, reticles are required to use optical proximity correction (OPC) and phase-shifted mask (PSM) for resolution enhancement. For OPC/PSM mask technology, defect printability is one of the major concerns. Current reticle inspection tools available on the market sometimes are not capable of consistently differentiating between an OPC feature and a true random defect. Due to the process complexity and high cost associated with the making of OPC/PSM reticles, it is important for both mask shops and lithography engineers to understand the impact of different defect types and sizes to the printability. Aerial Image Measurement System (AIMS) has been used in the mask shops for a number of years for reticle applications such as aerial image simulation and transmission measurement of repaired defects. The Virtual Stepper System (VSS) provides an alternative method to do defect printability simulation and analysis using reticle images captured by an optical inspection or review system. In this paper, pre- programmed defects and repairs from a Defect Sensitivity Monitor (DSM) reticle with 200 nm minimum features (at 1x) will be studied for printability. The simulated resist lines by AIMS and VSS are both compared to SEM images of resist wafers qualitatively and quantitatively using CD verification.Process window comparison between unrepaired and repaired defects for both good and bad repair cases will be shown. The effect of mask repairs to resist pattern images for the binary mask case will be discussed. AIMS simulation was done at the International Sematech, Virtual stepper simulation at Zygo and resist wafers were processed at AMD-Submicron Development Center using a DUV lithographic process for 0.18 micrometer Logic process technology.

Mask data volume: historical perspective and future requirements

Mask data file sizes are increasing as we move from technology generation to generation. The historical 30% linear shrink every 2-3 years that has been called Moores Law, has driven a doubling of the transistor budget and hence feature count. The transition from steppers to step-and-scan tools has increased the area of the mask that needs to be patterned. At the 130nm node and below, Optical Proximity Correction (OPC) has become prevalent, and the edge fragmentation required to implement OPC leads to an increase in the number of polygons required to define the layout. Furthermore, Resolution Enhancement Techniques (RETs) such as Sub-Resolution Assist Features (SRAFs) or tri-tone Phase Shift Masks (PSM) require additional features to be defined on the mask which do not resolve on the wafer, further increasing masks volumes. In this paper we review historical data on mask file sizes for microprocessor, DRAM and Flash memory designs. We consider the consequences of this increase in file size on Mask Data Prep (MDP) activities, both within the Integrated Device Manufacturer (IDM) and Mask Shop, namely: computer resources, storage and networks (for file transfer). The impact of larger file sizes on mask writing times is also reviewed. Finally we consider, based on the trends that have been observed over the last 5 technology nodes, what will be required to maintain reasonable MDP and mask manufacturing cycle times.

Detection of 60° phase defects on alternating PSMs

In this paper we present results of an algorithm that has been developed which is sensitive to phase defects of 60 degrees on i-line alternating PSMs. This algorithm consists of microcode and software, which can be loaded into existing inspection hardware. The algorithm works in die-to-die inspection mode and uses both transmitted and reflected light images to maximize sensitivity. Isolated phase defects as well as phase defects close to chrome edges were inspected. In addition, the algorithm is able to detect missing and mis-aligned shifter edges. A programmed phase defect test plate was developed to characterize defect detection sensitivity. Detection of 60 degrees defects smaller than 0.75 micrometers has been demonstrated with this algorithm. Defect sensitivity characterization and actual production plate effect results are shown. Finally, recent results showing the application of the algorithm to the inspection of Deep-UV multiphase reticles using a shorter inspection wavelength are presented.