John Lannon

Performance improvements in large format resistive array (LFRA) infrared scene projectors (IRSP)

Santa Barbara InfraRed (SBIR) is producing high performance 1,024 x 1,024 Large Format Resistive emitter Arrays (LFRA) for use in the next generation of IR Scene Projectors (IRSPs). The demands of testing modern infrared imaging systems require higher temperatures and faster frame rates. New emitter pixel designs, rise time enhancement techniques and a new process for annealing arrays are being applied to continually improve performance. This paper will discuss the advances in pixel design, rise time enhancement techniques and also the process by which arrays are annealed. Test results will be discussed highlighting improvements in rise time, uniformity and reduced numbers of defective pixels.

Advances in 3D integration of heterogeneous materials and technologies

Military applications demand more and more complex, multifunctional microsystems with performance characteristics which can only be achieved by using best-of-breed materials and device technologies for the microsystem components. Three-dimensional (3-D) integration of separate, individually complete device layers provides a way to build complex microsystems without compromising the system performance and fabrication yield. In the 3-D integration approach, each device layer is fabricated separately using optimized materials and processes. The layers are stacked and interconnected through area array vertical interconnects with lengths on the order of just tens of microns. This paper will review recent advances in development of 3-D integration technologies with focus on those which enable integration of heterogeneous materials (e.g. HgCdTe FPAs with silicon ROICs) or heterogeneous fabrication processes (e.g. resistive IR emitters with RIICs).

Large format resistive array (LFRA) infrared scene projector (IRSP) performance and production status

SBIR has completed development of the Large Format Resistive Array (LFRA) Infrared Scene Projector (IRSP) and shipped the first production system. Nine more systems are in production and will be shipped to several US Government customers on approximately six week centers. The commercial name of the LFRA IRSP is Mirage XL. System performance meets a broad range of program requirements and SBIR has been extremely successful in producing this ground breaking projector.

Scalable emitter array development for infrared scene projector systems

Several new technologies have been developed over recent years that make a fundamental change in the scene projection for infrared hardware in the loop test. Namely many of the innovations are in Read In Integrated Circuit (RIIC) architecture, which can lead to an operational and cost effective solution for producing large emitter arrays based on the assembly of smaller sub-arrays. Array sizes of 2048x2048 and larger are required to meet the high fidelity test needs of today’s modern infrared sensors. The Test Resource Management Center (TRMC) Test and Evaluation/Science and Technology (T and E/S and T) Program through the U.S. Army Program Executive Office for Simulation, Training and Instrumentations (PEO STRI) has contracted with SBIR and its partners to investigate integrating new technologies in order to achieve array sizes much larger than are available today. SBIR and its partners have undertaken several proof-of-concept experiments that provide the groundwork for producing a tiled emitter array. Herein we will report on the results of these experiments, including the demonstration of edge connections formed between different ICs with a gap of less than 10µm.

Low-cost uncooled VOx infrared camera development

The DRS Tamarisk® 320 camera, introduced in 2011, is a low cost commercial camera based on the 17 µm pixel pitch 320×240 VOx microbolometer technology. A higher resolution 17 µm pixel pitch 640×480 Tamarisk®640 has also been developed and is now in production serving the commercial markets. Recently, under the DARPA sponsored Low Cost Thermal Imager-Manufacturing (LCTI-M) program and internal project, DRS is leading a team of industrial experts from FiveFocal, RTI International and MEMSCAP to develop a small form factor uncooled infrared camera for the military and commercial markets. The objective of the DARPA LCTI-M program is to develop a low SWaP camera (<3.5 cm3 in volume and <500 mW in power consumption) that costs less than US

Ultra high temperature (UHT) infrared scene projector system development status

500 based on a 10,000 units per month production rate. To meet this challenge, DRS is developing several innovative technologies including a small pixel pitch 640×512 VOx uncooled detector, an advanced digital ROIC and low power miniature camera electronics. In addition, DRS and its partners are developing innovative manufacturing processes to reduce production cycle time and costs including wafer scale optic and vacuum packaging manufacturing and a 3-dimensional integrated camera assembly. This paper provides an overview of the DRS Tamarisk® project and LCTI-M related uncooled technology development activities. Highlights of recent progress and challenges will also be discussed. It should be noted that BAE Systems and Raytheon Vision Systems are also participants of the DARPA LCTI-M program.

OASIS: cryogenically-optimized resistive arrays and IRSP subsystems for space-background IR simulation

The Ultra High Temperature (UHT) development program will develop, package, and deliver high temperature scene projectors for the U.S. Government. The Infrared Scene Projector (IRSP) systems goals are to be capable of extremely high temperatures, in excess of 2000K, as well as fast frame rates, 500 Hz, and 2 ms rise times. The current status of the pixel design will be discussed with an emphasis on the models developed to facilitate these designs and estimate performance prior to fabrication.

Wafer-level 3D integration with 5 micron interconnect pitch for infrared imaging applications

SBIR has completed design and development of prototype emitter arrays and is completing custom cryogenic vacuum device packaging and support electronics for the Optimized Arrays for Space-background Infrared Simulation (OASIS) program. The OASIS array is a 512 x 512 device featuring high output dynamic range, a selectable analog/digital scene data interface, and the capability to operate from cryogenic to ambient substrate temperatures - thereby providing an enabling technology for projection of simulated radiance of space-background scenes. Prototype emitter production has been completed at RTI International in support of initial deliveries. The OASIS array package incorporates novel electrical bussing schemes optimized for the OASIS RIIC and a modular architecture to allow user re-configuration of both window and emitter shield. The OASIS package leverages LFRA operation features, and supports both ambient and cryogenic chamber-based operation with a minimum of mechanical and electrical re-configuration. The OASIS close support electronics (CSE) supports both analog and digital input data modes, while providing easy electronic connection between arrays installed in the cryogenic chamber and the external control and scene-generation systems. We present a technical overview of the OASIS array/package and CSE designs, and will report on measured radiometric performance from prototype OASIS arrays.

Heterogeneous microwave and millimeter-wave system integration using quilt packaging

The use of 3D integration technology in focal plane array imaging devices has been shown to increase imaging capability while simultaneously decreasing device area and power consumption, as compared to analogous 2D designs. A key enabling technology for 3D integration is the use of high density metal-metal bonding to form pixel-level interconnects between device layers. In this paper, we review recent progress in high density, sub-10 μm pitch interconnect bonding for 3D integration of imaging systems. Specifically, we will present results from successful demonstrations of the use of Cu microbumps for the interconnection of 5 μm pitch 640×512 and 1280×1024 arrays. Operability of the arrays of bonded interconnects in two-layer silicon die stacks was greater than 99.99% with good electrical isolation between bonds.

Ultrahigh-temperature emitter pixel development for scene projectors

Quilt Packaging (QP) is a direct chip-to-chip edge-interconnect technology that offers extremely low interconnect loss and can be implemented on a variety of substrates. We report here the experimental demonstration of heterogeneous integration between Si and GaAs substrates. Ultrawide-bandwidth Quilt Packaging coplanar waveguide interconnects between Si and GaAs chips are presented along with preliminary thermal shock data. Fabricated structures on ~100 μm thick Si and GaAs chips exhibited chip-to-chip insertion losses below 0.5 dB up to 170 GHz, and below 1 dB up to 220 GHz from on-chip S-parameter measurements. Simulated results on a heterogeneous Si-GaAs quilted chipset on scaled QP interconnect exhibited chip-to-chip insertion losses below 0.5 dB up to 300 GHz, and below 1.5 dB up to 750 GHz. Despite the coefficient of thermal expansion mismatch between Si and GaAs, the interconnects also exhibited no adverse effects from thermal shock testing through 1250 cycles.