John R. Goss

Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test

Use of a Scaling Parametric Macro (SPM) provides more accurate product level environment parametric information than scribe line (Kerf) structures. This paper compares drive current (Ion) data obtained with the SPM macros to scribe line structure Ion measurements. SPM macros provide less variation than scribe line structures. Since SPM is small enough to be included in all products, the SPM macro provides improved Ion product screening

Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable Memory

A memory sense-amplifier timing circuit emulates the behavior of weak memory tail-bits to improve Tail-Bit Tracking (TBT) across Process, Voltage and Temperature. The TBT circuit is used to generate timing for a search operation in a 32nm Ternary Content Addressable Memory (TCAM) compiler resulting in 200mV Vmin improvement at a constant performance, and 50% improved search-time performance at a constant Vmin. This TBT circuit was implemented in 32nm High-K Metal Gate SOI process to achieve 0.60V operation and support up to 1G search/sec throughput on a 2048×640bit TCAM instance.

Improved yield through use of a Scalable Parametric Measurement macro

Incorporating a scalable parametric measurement (SPM) macro in semiconductor products enables N to P ratio screening at wafer test where each die can be tested. While in line scribe line measurements provide valuable feedback to correct manufacturing problems, in line test sample sizes and the need to disposition entire wafers limit the usefulness of this technique as a product screen. Functional patterns applied at module test provide a measure of protection against escapes to system level, but module yield loss results in higher cost than wafer yield loss because of the added loss of package and module test costs. Use of a SPM macro for N to P ratio disposition maximizes yield and minimizes false rejects and false accepts.