John Rozen

Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths

High-Ge-content (HGC) SiGe FinFETs in a “replacement High-K and metal-gate” (RMG) process flow and with aggressive EOT scaling are demonstrated, for the first time. HGC SiGe pMOS FinFETs with high-mobility, record-low RMG long-channel SS=66mV/dec and great short-channel characteristics down to L_G=21nm have been demonstrated. Gate stack and transport properties down to sub-4nm fin widths (W_FIN) have been also studied for the first time. We demonstrate excellent RMG mobility and reliability at aggressive EOT~7Å, and excellent μ_eff=220cm²/Vs at N_inv=10¹³ for fins with W_FIN~4nm, outperforming state-of-the-art devices at such dimensions and providing very promising results for FinFET scaling for future high-performance FinFET generations.

High Mobility High-Ge-Content SiGe PMOSFETs Using Al 2 O 3 /HfO 2 Stacks With In-Situ O 3 Treatment

We developed an Al₂O₃/HfO₂ bi-layer gate dielectric with an <italic>in-situ</italic> O₃ treatment for interface state density (D_it) and gate leakage current density (J_g) reductions on SiGe channels. We observed Ge-content dependent equivalent oxide thickness (EOT) scaling and EOT 0.44 nm was achieved with an MOS capacitor with a Si_0.05Ge_0.95 substrate. The O₃ treatment enabled application to non-planar device structures and we demonstrated five orders of magnitude lower off currents (I_OFF), a sub-threshold slope of 68 mV/decade, and a very high hole mobility of 457 cm<inline-formula> <tex-math notation=LaTeX>

High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length

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Electrical characterization of FinFETs with fins formed by directed self assembly at 29 nm fin pitch using a self-aligned fin customization scheme

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Electron mobility in thin In 0.53 Ga 0.47 As channel

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High-performance CMOS-compatible self-aligned In 0.53 Ga 0.47 As MOSFETs with GMSAT over 2200 µS/µm at V DD = 0.5 V

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PBTI in InGaAs MOS capacitors with Al 2 O 3 /HfO 2 /TiN gate stacks: Interface-state generation

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COMBINED REACTIVE GAS SPECIES FOR HIGH-MOBILITY CHANNEL PASSIVATION

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BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS

We report the fabrication of short-channel FinFETs on InGaAs-on-silicon wafers using the aspect ratio trapping (ART) technique. We demonstrate excellent short-channel control down to 20 nm gate length due to scaled fin width down to 9 nm and reduction of parasitic bipolar effect (PBE). PBE that plagues III-V NFETs with gate-all-around (GAA) or III-V-on-insulator (III-V-OI) structures can be significantly suppressed by optimized ART FinFET technology. We demonstrate record high on-current ION and low drain leakage current for short gate lengths in the 20–32 nm range for InGaAs-on-silicon NFETs.

Electron mobility in thin In0.53Ga0.47As channel.

In this work, we report electrical characterization FinFET devices with 29nm-pitch fins patterned using a technique called tone inverted grapho-epitaxy (TIGER). We use a topographic template to direct the self-assembly of block copolymers (BCP) to form small area gratings that are self-aligned to the template. After a tone-inversion operation, blocks of defect free SOI fins bounded by self-aligned exclude regions are formed with the spacing determined by the template line width (LW). This self-aligned customization enables further definition of the active region for FinFETs. Process window and design implications for directed self-assembly (DSA) with TIGER are also discussed.