John Y. Chen

CMOS — The emerging VLSI technology

The recent evolution in CMOS as the emerging very-large-scale-integrated (VLSI) circuit technology is reviewed. Various CMOS technologies and their impact on circuit performance and reliability are discussed and compared in generic and special circuit applications. Key issues in CMOS scaling, such as hot-electron effects, buried-channel characteristics, latchup, and isolation requirements, are briefly described. State-of-the-art CMOS design rules are also addressed. Future trends of CMOS technology development in VLSI circuits are discussed.

Three-dimensional effects in CMOS latch-up

The influence of three-dimensional effects on latch-up in n well CMOS circuits fabricated on both bulk and p on p+ epitaxia substrate material is reported. It is demonstrated that narrow-width phenomena can play a dominant role in determining the latch-up performance of CMOS devices, and give rise to large deviations from ideal scaling with width. This limits the applicability of two-dimensional models, and also means that the latch-up behavior of real circuits may differ significantly from predictions based on the performance of test structures. A simple approach to modeling the three-dimensional phenomena is also presented.

A new process for one micron and finer CMOS

We have demonstrated a new process architecture using retrograde N-wells which provides rigorous isolation and latch-up immunity at 3µm N+to P+spacing, while using straightforward LOCOS processing with self-aligned channel stops. Excellent transistor performance has been obtained. Twenty-three stage ring oscillators with and without LDD structure have been characterized.