Jon D. Cheek

Effect of local interconnect etch-stop layer on channel hot-electron degradation

Routine use of an etch-stop layer during semiconductor processing favors circuit density and performance through the use of local interconnect and similar damascene processes, and also allows the use of manufacturable etch recipes. Previous studies have demonstrated that post transistor definition, topside passivation and deposition techniques can significantly impact device degradation characteristics. This work further investigates the choice of local interconnect etch-stop layer and its effect on channel hot-electron degradation. A reduction in channel hot-electron degradation is demonstrated through the use of N2O anneal gate oxide, and using experimental data a possible degradation mechanism, caused by the presence of the etch-stop layer, is identified. A brief review of the compatibility of etch-stop layers with high performance 0.3 micrometer CMOS devices is presented through interface state and hot-electron stress measurements.

Improved p-ch MOS transistor performance with an arsenic supersteep retrograde channel profile

The benefits of super steep retrograde channel profiles on MOS transistor performance as reported in the literature have been inconsistent. This inconsistency is in part due to the sensitivity of the performance benefit to the process parameters and integration of the retrograde channel profile. As exhaustive study that integrated and optimized a p-ch arsenic retrograde channel profile transistor into a high performance sub 0.18micrometers transistor CMOS microprocessor process was performed. It was found that the dose and energy of the retrograde channel implant significantly affected the performance improvement obtained. A higher SSRC implant dose, or lower implant energy resulted in higher drive current for a given off current relative to a conventional channel profile control transistor. In addition, the improvement in the transistor linear current was even more significant. At IDOFF equals 1nA, the IDS and IDLIN improvement was approximately 10 percent and 16 percent, respectively. Improvement in transistor drive current also increased at higher drive current. The saturated threshold voltage and Drain Induced Barrier Lowering roll-off with effective channel length were superior for the retrograde channel profile versus the conventional channel profile transistor. Gate oxide reliability with the arsenic doping was also evaluated using Voltage Ramped Dielectric Breakdown (VRDB). It was found that the p-ch gate oxide capacitor VRDB failure rate with the arsenic retrograde channel doping profile was as good or better compared with the conventional phosphorous doped channel profile.

Device performance and optimization for 5th- and 6th-generation microprocessors

A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.