Mark I. Gardner

Sub 2 nm Thick Zirconium Doped Hafnium Oxide High-K Gate Dielectrics

Zr-doped HfOx high-k gate dielectric films with TiN gate electrode were sputter deposited on 1 nm SiO2 or SiOxNy interface layer. Electrical properties including the equivalent oxide thickness, flat band voltage, interface state density, and the oxide charge trapped density of the MOS capacitors were investigated with respect to fabrication parameters such as Zr doping condition, post deposition annealing ambient, and type of bottom interface layer. Excellent electrical properties were obtained for films deposited at low sputtering powers. An equivalent oxide thickness of 1.7 nm was achieved for Zr-doped HfOx on a 1 nm SiO2 interface. The leakage current is four orders of magnitude lower than that of the SiO2 film. The magnitude and polarity of the flat band voltage is influenced by the high-k film deposition method, the dopant concentration, and the post deposition annealing condition. With the same SiOxNy interface layer, the Zr-doped film has a lower leakage current and a smaller interface density of states than the undoped film.

Electrical properties of amorphous high-/spl kappa/ HfTaTiO gate dielectric with dielectric constants of 40-60

High-quality Hf-based gate dielectrics with dielectric constants of 40-60 have been demonstrated. Laminated stacks of Hf, Ta, and Ti with a thickness of /spl sim/10 /spl Aring/ each was deposited on Si followed by rapid thermal anneal. X-ray diffraction analysis showed that the crystallization temperature of the laminated dielectric stack is increased up to 900/spl deg/C. The excellent electrical properties of HfTaTiO dielectrics with TaN electrode have been demonstrated, including low interface state density (D/sub it/), leakage current, and trap density. The effect of binary and ternary laminated metals on the enhancement of dielectric constant and electrical properties has been studied.

Correlation of dielectric breakdown with hole transport for ultrathin thermal oxides and N2O oxynitrides

In this letter, the dielectric breakdown characteristics of thermal oxides and N2O‐based oxynitrides have been studied. A direct correlation was found between dielectric breakdown and the hole current generated within the gate dielectrics. The dependence of dielectric breakdown on oxide thickness was also studied. It was found that both charge‐to‐breakdown and hole‐fluence‐to‐breakdown for the N2O oxynitrides were higher than those for the thermal oxides throughout the thickness range studied (33–87 A). The results suggest that N2O oxynitrides can sustain more damage before breakdown and thus have superior dielectric integrity compared to the thermal oxides.

Effects of Structural Properties of Hf-Based Gate Stack on Transistor Performance

Electron traps in ALD and MOCVD HfO 2 and HfSiO high-k dielectrics were investigated using both conventional DC and pulse measurements. It was found that the traps in the gate stack could be associated with defects of different activation energies and capture cross-sections. This points to potentially different origins of the electrically active defects, which can be either intrinsic or process-related. Structural non-uniformity of the high-k film, associated with grain formation and phase separation, may lead to variation of electrical properties of the gate dielectric along the transistor channel. Effects of such dielectric non-uniformity, as well as electron trapping, on the measured transistor mobility were evaluated.

Experimental study of etched back thermal oxide for optimization of the Si/high-k interface

We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

Impacts of gate electrode materials on threshold voltage (V/sub th/) instability in nMOS HfO/sub 2/ gate stacks under DC and AC stressing

Ultrathin nMOSFET hafnium oxide (HfO/sub 2/) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-/spl kappa/ interface exhibits more traps due to interfacial reaction than the TiN/high-/spl kappa/ interface, resulting in significantly worse dc V/sub th/ instability. However, the V/sub th/ instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G/sub m/ degradation.

‘‘Turn‐around’’ effects of stress‐induced leakage current of ultrathin N2O‐annealed oxides

Studies of the thickness dependence on stress‐induced leakage current (SILC) have been performed in the thickness range of 41 to 87 A for N2O‐annealed and O2‐grown oxides. N2O‐annealed oxide shows significantly reduced SILC leakage currents. Furthermore, SILC currents were found to increase with decreasing oxide thickness, as reported earlier. However, a ‘‘turn‐around’’ effect at ∼50 A has been observed in these films. SILC currents begin to decrease when oxide thickness is scaled below 50 A. This turn‐around effect can be explained using the trap‐assisted tunneling model. For thicknesses equal or less than 41 A, defect‐related current and direct tunneling current become dominant over SILC current. Our results indicated that for N2O‐based oxides in the ultrathin thickness regime, stress‐induced leakage currents become less significant.

Integration issues of high-k gate stack: Process-induced charging

Electrical properties of a wide range of Hf-based gate stacks were investigated using several modifications of a standard planar CMOS process flow to address the effects of transistor processing on the electrical properties of the high-k dielectrics. Characteristics of the short channel transistors were shown to be very sensitive to the fabrication process specifics - process sequence, tools, and recipes. It was concluded that, contrary to SiO/sub 2/, the high-k films could be contaminated with reactive species during the post-gate definition fabrication steps, resulting in the formation of local charge centers. Such process-induced charging (PIC) degrades transistor performance and complicates evaluation of the intrinsic properties of high-k dielectrics. A process scheme that minimizes PIC is discussed.

Improved device performance and reliability in high /spl kappa/ HfTaTiO gate dielectric with TaN gate electrode

The device performance and reliability of higher-/spl kappa/ HfTaTiO gate dielectrics have been investigated in this letter. HfTaTiO dielectrics have been reported to have a high-/spl kappa/ value of 56 and acceptable barrier height relative to Si (1.0 eV). Through process optimization, an ultrathin equivalent oxide thickness (EOT) (/spl sim/9 /spl Aring/) has been achieved. HfTaTiO nMOSFET characteristics have been studied as well. The peak mobility of HfTaTiO is 50% higher than that of HfO/sub 2/ and its high field mobility is comparable to that of HfSiON with an intentionally grown SiO/sub 2/ interface, indicative of superior quality of the interface and bulk dielectric. In addition, HfTaTiO dielectric has a reduced stress-induced leakage current (SILC) and improved breakdown voltage compared to HfO/sub 2/ dielectric.

Time Dependence of Phosphorus Diffusion and Dose Loss during Postimplantation Annealing at Low Temperatures

Transient enhanced diffusion (TED) of implanted phosphorus was extensively investigated under various ion implantation and annealing conditions. The effective diffusivities of each annealing time period were determined to study the evolution of TED under low-temperature annealing. It was found that TED decays at the early stage of low-temperature annealing until diffusion enhancement reaches a steady state. Further annealing causes a significant decrease of diffusivity as TED is completed. It was also found that higher implantation energy enhances diffusion because of slower decay of TED. However, higher implantation dose introduces more diffusion enhancement without changing the decay behavior of TED. Severe dose loss was observed during the TED period. It was found that the dose loss is controlled by TED. As a result, higher annealing temperature and longer annealing time lead to greater phosphorus dose loss.