Jonas Lindstrand

A 1.6–2.6GHz 29dBm injection-locked power amplifier with 64% peak PAE in 65nm CMOS

This paper presents a wideband CMOS power amplifier intended for cellular handset applications. The circuit exploits injection locking to achieve a power gain of 20.5dB from a single stage amplifier. The maximum output power of 29dBm, with a peak drain- and power-added-efficiency (PAE) of 66% and 64%, respectively, occurs at a center frequency of 2GHz with a 3V supply. A cross-coupled cascode topology enables a wideband PAE exceeding 50% from 1.6 to 2.6GHz. For output power levels below 4dBm the circuit operates as a linear class AB amplifier with a power consumption of 17mW from a 0.48V supply. The power gain of 20.5dB is kept constant for all output powers; with an AM-AM- and AM-PM-conversion of 0.2dB and 17deg, respectively, over the entire WCDMA dynamic range of 80dB. The circuit is implemented in a standard 65nm CMOS process with a total chip area of 0.52×0.48mm2 including pads.

A low band cellular terminal antenna impedance tuner in 130nm CMOS-SOI technology

This paper presents a low band antenna impedance tuner in 130nm CMOS-SOI technology. It consists of three digitally controlled switched capacitor banks and two off-chip inductors and is intended for use in terminals supporting modern cellular standards like WCDMA and LTE. By using a negative gate bias in the off state, linearity can be improved and maintained. Measurements show an OIP3 exceeding +55dBm for all measured impedance states, which cover a VSWR of up to 5.4. The measured minimum loss is 1dB or lower in the frequency range from 700-900MHz with spurious emissions below -30dBm at +33dBm input power. The switched capacitors are implemented with eight stacked transistors to yield a voltage handling of at least 20V, and in order to handle the large voltages custom designed capacitors are used.

An Integrated 3-Level Fully Adjustable PWM Class-D Audio Amplifier in 0.35μm CMOS

A class-D audio amplifier utilizing a fully adjustable 3-level pulse width modulation (PWM) is presented. The amplifier is fully integrated in a 0.35 μm CMOS process, and is powered by a 3.3 V power supply. The system includes an internal fully adjustable triangle-wave oscillator, which is used to generate the PWM carrier. Delivering an output power of 300 mW is a differential bridge (7.5 cm pMOS, 3 cm nMOS), driving a 16 Ω load. The THD+N of the system is less than 0.2%, and the efficiency at 300 mW is 89%.

Experimental Investigation of Adaptive Impedance Matching for a MIMO Terminal With CMOS-SOI Tuners

It is well known that user proximity introduces absorption and impedance mismatch losses (MLs) that severely degrade multiple-input multiple-output (MIMO) performance of handset antennas. In this work, we experimentally verified the potential of adaptive impedance matching (AIM) to mitigate user interaction effects and identified the main AIM gain mechanism in realistic systems. A practical setup including custom-designed CMOS silicon-on-insulator (SOI) impedance tuners implemented on a MIMO handset was measured in three propagation environments and ten real user scenarios. The results indicate that AIM can improve MIMO capacity by up to 42% equivalent to 3.5 dB of multiplexing efficiency (ME) gain. Taking into account the measured losses of 1 dB in the integrated tuners, the maximum net ME gain is 2.5 dB suggesting applicability in practical systems. Variations in ME gains of up to 1.5 dB for different hand-grip styles were mainly due to differences in impedance mismatch and tuner loss distribution. The study also confirmed earlier results on the significant differences in mismatch and absorption between phantoms and real users in which the phantoms underestimated user effects and, therefore, AIM gains. Finally, propagation environments of different angular spreads were found to give only minor ME gain variations.

A 70 and 210 GHz LO generator in 65nm CMOS

A CMOS LO-Generator operating at 70GHz and 210GHz by the use of a frequency tripling technique is presented. A cross-coupled NMOS VCO is used together with a single-balanced mixer to achieve low phase-noise. The chip measures a single-ended output power of -15dBm in the 70GHz band, with 6.54% tuning range, from a 1.2V supply while consuming 7.2mW. A phase-noise of -113.2dBc/Hz is measured at 10MHz frequency offset from a carrier frequency of 73.8GHz. This yields a phase noise figure of merit, FOM, of 181.8dB, and with the tuning range taken into account, a FOMT of 178dB. By using this technique neither FOM nor FOMT are degraded in the 210GHz band since both power consumption and tuning range are maintained.