Joongjin Nam

A highly linear and efficient differential CMOS power amplifier with harmonic control

A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-/spl mu/m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g/sub m3/ and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5dBm of P/sub 1dB/ with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under -45 dBc of IMD3 and -57dBc of IMD5 when the output power is backed off by more than 5dB from P/sub 1dB/. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification.

Measurement of two-tone transfer characteristics of high-power amplifiers

In this paper, we present an accurate measurement method for acquiring the two-tone transfer characteristics of high-power amplifiers. The measurement setup and sequence are described. The measured amplitude and phase data of the two-tone fundamental, third-order intermodulation, and fifth-order intermodulation components versus input power level are also presented. The measured two-tone transfer characteristics are very useful for the design of a predistortion linearizer or for nonlinear model extraction for high-power amplifiers.

A handset power amplifier with high efficiency at a low level using load-modulation technique

A new monolithic-microwave integrated-circuit power amplifier for cellular handsets has been implemented using the load-modulation concept of the Doherty amplifier, which has a high efficiency at a low power level. In order to get a compact module, the /spl lambda//4 transmission line for the load modulation is replaced by a passive high-pass /spl pi/-network, and the load-modulation circuit is also modified to function as a power-matching circuit of the main amplifier. The amplifier has two modes of operation, low- and high-power modes, controlled by a control voltage. At the high power mode, both the main and auxiliary amplifiers are operational and, at the low power mode, only the main amplifier generates output power enhancing the efficiency. For the code-division multiple-access environment, the amplifier at the low-power mode provides power-added efficiency (PAE) of 39.8% and an adjacent channel power ratio (ACPR) less than 49.8 dBc at 23.1 dBm, and the high-power mode PAE of 37.9% and ACPR of 46.4 dBc at 28 dBm. The efficiency is improved by approximately 18.8% at P/sub out/=23 dBm by the load-modulation technique. For the advanced mobile phone system-mode operation, the amplifier delivers 26.1 dBm with PAE of 53% and 30.8 dBm with 48.7% at the low and high modes, respectively.

The Doherty Power Amplifier With On-Chip Dynamic Bias Control Circuit for Handset Application

A monolithic-microwave integrated-circuit Doherty power amplifier (PA) with an on-chip dynamic bias control circuit for cellular handset application has been designed and implemented. To improve the linearity and efficiency in the operation power ranges, the base and collector biases of the amplifiers, except the drive amplifier of the main path, are controlled according to the average output power. The base biases are controlled using the on-chip circuit and collector biases by the dc/dc chip to reduce the average dc consumption power. The power-added efficiency (PAE) is improved approximately 6% by the base dynamic bias control, and approximately 14% by the collector/base dynamic control from the class AB at Pout=16 dBm, respectively. If the dc/dc converter efficiency is 100%, the PAE could be improved approximately 17.5% from class AB, reaching to 29.2% at Pout=16 dBm. In the intermediate power level from 22 to 28 dBm, the PAE is over 34.3%. The average current consumption of the PA with the dynamic bias control is 22.5 mA in urban and 37.3 mA in suburban code-division multiple-access environments, which are reduced by 36%-46.7%, compared to the normal operation. The adjacent channel power ratio is below 47.5 dBc, and the PAE at the maximum power is approximately 43.3% in the dynamic bias operations

Digital controlled adaptive feedforward amplifier for IMT-2000 band

We present a broadband adaptive control method for IMT-2000 band multi-carrier power amplifiers adopting feedforward linearization. We have analyzed and implemented an error cancellation detection method employing a frequency hopping pilot and IF synchronous sampling correlator with DSP controller. An adaptive delta-modulated power gradient algorithm is used to adjust the signal and error cancellation loop control parameters. A 2.15 GHz feedforward power amplifier with digital controller is implemented. Band test results show that it covers over a 90 MHz band with more than 50 dBc of IMD at 5 MHz offset frequency for an 8.3 MHz WCDMA signal. The adaptation result shows very fast convergence.

Feedforward amplifier for WCDMA base stations with a new adaptive control method

This paper describes a feedforward amplifier with a new adaptive control method. For the modulated signal with a high peak-to-average ratio, the residual output error level of the feedforward amplifier can be further reduced by adjusting the 1st loop control parameters to have an imperfect signal cancellation since an error amplifier generates less distortion in the case. For verification, a baseband signal simulation and experiments have been performed. A 30 W feedforward amplifier for WCDMA base stations at 2.14 GHz shows a 4 dB improvement of linearization when it is controlled by the proposed method.

Doherty Linear Power Amplifiers for Mobile Handset Applications

Two Doherty amplifiers are designed in MMIC form, which are fabricated using a commercial InGaP/GaAs HBT foundry process. The one is classical Doherty type amplifier with the size ratio of main device and auxiliary device of N=l, and the other is an extended Doherty with the size ratio of N=3. The input and output circuits are made using hybrid circuit, forming power amplifier modules. The efficiencies are improved about 18.8% at Pout = 23 dBm, about 5 dB backed-off point, from the size ratio N=l amplifier, and about 21% at Pout = 18.6 dBm, about 10 dB backed-off point, from the size ratio N=3 one. We have extended the technology to the fully integrated power amplifier chip. The amplifier shows an output power of 22.5 dBm and a power-added efficiency (PAE) of 21.3% at an error vector magnitude (EVM) of 5%, measured with 54 Mbps 64-QAM- OFDM signals at 5.2 GHz.

Doherty linear power amplifiers for mobile handset applications

Two Doherty amplifiers are designed in MMIC form, which are fabricated using a commercial InGaP/GaAs HBT foundry process. The one is classical Doherty type amplifier with the size ratio of the main device and auxiliary device of 1(N = 1), and the other is an extended Doherty with the size ratio of 3(N = 3). The input and output circuits are made using a hybrid circuit, forming power amplifier modules. The efficiencies are improved about 18.8% at Pout = 23 dBm, about 5 dB backed-off point, from the size ratio N = 1 amplifier, and about 21% at Pout = 18.6 dBm, about 10 dB backed-off point, from the size ratio N = 3 one. We have extended the technology to the fully integrated power amplifier chip. The amplifier shows an output power of 22.5 dBm and a power-added efficiency (PAE) of 21.3% at an error vector magnitude (EVM) of 5%, measured with 54 Mbps 64-QAM-OFDM signals at 5.2 GHz