Joonhoi Hur

Peaking PA bias circuit for an APT CMOS Doherty PA

This paper presents a peaking PA bias circuit for an Average Power Tracking (APT) CMOS Doherty PA, where the common supply voltage changes as the target average power changes. In order to have Doherty efficiency characteristics with APT, the peaking PA must have an adaptive bias circuit that shifts the bias as the supply voltage changes, activating the peaking PA at the correct backoff (6dB) from the Posat for that supply voltage. This bias circuit is demonstrated on a CMOS Doherty PA using standard 0.18um SOI. With the proposed bias circuit, the Doherty PA has specification compliant WCDMA performance (with DPD) up to 29dBm Pout, with 40–50% PAE (from 25–29dBm Pout) as the supply voltages ranges from 1.5V to 4V.

A multi-band CMOS Doherty PA with tunable matching network

This paper present a multi-band Doherty power amplifier (DPA) implemented in a 0.18um CMOS SOI. In order to enable the multi-band operation, the proposed DPA employs tunable matching networks with digital controls that are set via serial RFFE commands. Using digital pre-distortion (DPD) techniques, the proposed Doherty PA improves efficiency over a wide output power range and over multiple bands of operation. By utilizing linearizer circuits, tunable matching networks and DPD, the measured PAE with the R99 modulated signal can be as high as 50.1% at 27.8dBm output power while meeting ACP specifications.

A 5.5-GHz CMOS power amplifier using parallel-combined transistors with cascode adaptive biasing for WLAN applications

This paper presents a fully integrated power amplifier (PA) using parallel-combined transistors with a cascode adaptive biasing, implemented in a standard 65 nm CMOS process. The parallel-combined transistors in the common-source stage linearizes the effective gm. In addition, adaptive bias circuits are applied to both the common-source and common-gate stages to provide optimum operation conditions to each transistor, according to the output power variations. When the fully integrated PA was tested with a modulation and coding scheme 7 (MCS7) 802.11n signal, it meets a −28 dB error vector magnitude and spectral mask requirements at 18.4 dBm of average output power, with a power-added efficiency of 13.1%.

A Multilevel Class-D CMOS Power Amplifier for an Out-Phasing Transmitter With a Nonisolated Power Combiner

This brief presents a nonisolated multilevel linear amplifier with nonlinear component (LINC) power amplifier (PA) implemented in a standard 0.18-μm complementary metal-oxide- semiconductor process. Using a nonisolated power combiner, the overall power efficiency is increased by reducing the wasted power at the combined out-phased signal; however, the efficiency at low power still needs to be improved. To further improve the efficiency of the low-power (LP) mode, we propose a multiple-output power-level LINC PA, with load modulation implemented by switches. In addition, analysis of the proposed design on the system level as well as the circuit level was performed to optimize its performance. The measurement results demonstrate that the proposed technique maintains more than 45% power-added efficiency (PAE) for peak power at 21 dB for the high-power mode and 17 dBm for the LP mode at 600 MHz. The PAE for a 6-dB peak-to-average ratio orthogonal frequency-division multiplexing modulated signal is higher than 24% PAE in both power modes. To the authors knowledge, the proposed output-phasing PA is the first implemented multilevel LINC PA that uses quarter-wave lines without multiple power supply sources.