Hyoungsoo Kim

Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections

Limitations in current backplane environments impede high-speed data transmission above 5 Gb/s. A system architecture to extend the transmission capacities of legacy backplanes is proposed. The incentives for using a four-level pulse amplitude modulation (4-PAM) scheme are also presented. The architecture is built from feed-forward equalizer and tunable filter elements for near-end crosstalk noise cancellation. Each of the circuits is implemented in a standard 0.18-/spl mu/m CMOS process. The building blocks of the architecture, which include an LC ladder, a modified Gilbert-cell multiplier with improved headroom, and a tunable active high-pass filter are described in detail. Results of the architecture are shown demonstrating 20-Gb/s 4-PAM signal transmission.

0.18-/spl mu/m CMOS equalization techniques for 10-Gb/s fiber optical communication links

Limitations in data transmission caused by modal dispersion in fiber-optic links can be significantly improved using equalization techniques. In this paper, two different equalizer implementation approaches are proposed to extend the transmission capacities of existing fiber-optic links. The building blocks of the equalizer including a multiplier cell, a delay line, and an output buffer stage are fully integrated on a 0.18-/spl mu/m CMOS process. For the continuous-time tap-delay implementation, a passive LC delay line and an active inductance peaking delay line are compared for performance against process variation, as well as power consumption. In addition, a delay-locked loop is proposed to counter delay variations caused by changes in the process corner. A 10-Gb/s nonreturn-to-zero signal is received after transmission through a 500-m multimode-fiber channel, and the signal impairment due to the differential modal delay is successfully compensated using both feed-forward equalizers.

A Wideband Low-Power CMOS LNA With Positive–Negative Feedback for Noise, Gain, and Linearity Optimization

A wideband common-gate (CG) low-noise amplifier (LNA) utilizing positive-negative-feedback technique is presented. The positive-negative-feedback technique boosts effective transconductance (Gm) and output impedance, which leads to an LNA with higher gain and lower noise figure (NF) over the previously reported amplifiers. In addition, this approach provides high linearity with an aid of third harmonic cancellation, and it breaks transconductance (gm) constriction for input matching in CG amplifiers. In this paper, linearity and output impedance improvement through the proposed technique are fully analyzed. An LNA prototype is implemented in 0.18- μm CMOS technology occupying a total area of 0.33 mm2. The implemented LNA delivers a maximum voltage gain of 21 dB, a minimum NF of 2 dB, an third-order intermodulation intercept point of -3.2 dBm, and 3.6 mW of power consumption in 300-920 MHz of 3-dB bandwidth with input matching (S11 <; -10 dB).

A 10-Gb/s Reconfigurable CMOS Equalizer Employing a Transition Detector-Based Output Monitoring Technique for Band-Limited Serial Links

Limitations in data transmission caused by band limitation in broadband communication links can be improved significantly by using equalization techniques. In this paper, a reconfigurable feed-forward equalizer employing a transition detector (TD)-based calibration technique that provides a universal channel compensation solution is presented. Moreover, the newly proposed TD-based calibration technique monitors the channel output for further adjustments over time in order to provide optimum compensation in performance. The reconfigurable equalizer is implemented in a 0.18-mum CMOS technology. The prototype successfully demonstrates the feasibility of the TD-based calibration technique for output monitoring

A 0.25-um BiCMOS Feed Foward Equalizer Using Active Delay Line for Backplane Communication

In this paper, a BiCMOS equalizer using an active delay line structure for backplane communication is investigated. Equalization is achieved using a finite impulse response (FIR) filter. The filter is implemented using variable gain blocks and delay elements. The variable gain function is implemented using a Gilbert cell topology, modified for high-speed application. The delay line is implemented using active devices. The active delay line consumes less area than a passive L-C delay line, and has improved bandwidth as well as performance over process variation. The equalizer is implemented in a 0.25-mum BiCMOS technology. To the best our knowledge, it is the first BiCMOS equalizer using an active delay line approach.

Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology

In order for adaptive filter design to achieve optimum performance, the latency around the loop needs to be exactly designed for each targeted data rates. Due to unforeseen parasitic effects, latency has been major design issues for adaptive filters design with decision feedback topologies. In this paper, a digitally controlled adjustable delay line IC is presented that can be tuned with 3-ps resolution with a modular-based digital-to-analog converter (DAC) design. The proposed adjustable delay line achieved wide bandwidth for 10-Gb/sec data throughput while demonstrating bit-error rate (BER) improvement for the given equalizer design over various band-limited channels. The proposed IC is implemented in a 0.18-mum standard CMOS technology.

Electrical Dispersion Compensator for a Giga-bit Passive Optical Network System with Fabry-Perot Laser

In this paper, we present an electrical dispersion compensator (EDC) for a 1.25 Gb/s gigabit passive optical network (GPON) with Fabry-Perot (FP) lasers. Due to mode-partition noise (MPN) from the FP laser and fiber dispersion, GPON systems suffer from inter-symbol interference (ISI). The choice of the architecture for the EDC is a feed-forward equalizer (FFE) structure. The GPON experimental link was set-up with 0~15km fiber with a commercial triplexer. The EDC successfully compensates ISI for a given link with a 1.25 Gb/s PRBS signal. The EDC is implemented in 0.18 um CMOS technology with 54 mW power consumption from a 1.8 V power supply.

A Reconfigurable 0.18-μm CMOS Equalizer IC with an Improved Tunable Delay-Line for 10-Gb/sec Backplane Serial I/O Links

In this paper, a reconfigurable CMOS equalizer is presented to accommodate vast variety of backplane channel loss characteristics. Backplane channels over different trace lengths and dielectric materials were measured and characterized. Feed-forward equalizer (FFE) topology with finite impulse response (FIR) architecture was chosen for optimal equalization for the corresponding backplane configurations. For a reconfigurable FFE IC implementation, wide-range tunable delay-line (15-ps ~ 74-ps) and variable tap-gain amplifier were fabricated in a 0.18-mum standard CMOS technology. The proposed reconfigurable FFE demonstrated successful equalization at 10Gb/sec over various channel configurations with 26mW power dissipation from a 1.8-V supply

A 10Gb/s two dimensional scanning eye opening monitor in 0.18um CMOS process

An eye-opening monitor (EOM) capable of providing qualitative two-dimensional (2D) map of the eye opening of a 10Gbps signal is designed. The EOM is designed in 0.18 um CMOS process. The 2D map of the eye opening is obtained by scanning the eye opening with a phase-offset clock to obtain the different best-fit mask sizes. In the present design the clock is provided from an external source. The design operates with a 1.8V supply and consumes 95 mA of current.

Performance analysis of feed-forward equalizers based on passive and active delay cells for multi-Gb/s optical fiber links

In this paper, two 9-taps FFE structures using different delay cell approaches are implemented and analyzed. The first FFE uses passive delay cells based on an artificial transmission line implemented using an inductor-capacitor (LC) ladder, and the second FFE uses active delay cells implemented with differential pairs incorporating an active inductive peaking technique.